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datasheet portable consumer codec low-power, high-fidelity integrated codec acs522d01 1 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 description the acs522d01 is a low-power, high-fidelity integrated codec targeted at portable applications such as tablet computers, personal navigation devices, portable projec- tors and speaker docks. in addition to a high-fidelity low-power codec, th e device integrates a true cap-less headphone amplifier. beyond hi gh-fidelity for portable sys- tems, the device offers an enriched ?audio presence? through built-in audio processing capability. target applications ? tablet computers ? portable navigation devices ? personal media players ? portable projectors ? speaker docks features ? high fidelity 24-bit stereo codec ? dac 102db snr; thd+n better than -82db ? adc 90db snr, thd + n better than -80db ? built in audio controls and processing ? 3d stereo enhancement ? dual (cascaded) stereo 6-ba nd parametric equalizers ? programmable compressor/limiter/expander ? psychoacoustic bass and treble enhancement processing ? on-chip true cap-less headphone driver ? 35 mw output power (16 ? ) ? charge-pump allows true ground centered outputs ? snr of 102db ?i2s data interface ? microphone/line-in interface ? 2 analog inputs for analog microphone or line-in support ? 1 digital input for digital microphone support ? automatic level control ? on-chip low-jitter pll for audio timing ? low power with built in power management ? 1.7 v codec supports 1vrms ? very low standby and no-signal power consumption ? 1.8v digital / 1.7v analog supply for low power ? 2-wire (i 2 c compatible) control interface ? 41-ball wlcsp rohs package
2 v0.5 04/11 ?2011 integrated device technology, inc. acs522x01 acs522x01 low-power, high-fidelity, integrated codec table of contents 1. overview ................................................................................................................... ............. 7 1.1. block diagram ............................................................................................................ .......................7 1.2. audio outputs ............................................................................................................ ........................7 1.3. audio inputs ......... .............. .............. .............. .............. ........... ............ ........... .......... ..........................8 2. power management .......................................................................................................... 9 2.1. control registers ........................................................................................................ .......................9 2.2. stopping the master clock ................................................................................................ .................9 3. output audio processing ............................................................................................. 10 3.1. dc removal ............................................................................................................... .....................10 3.2. volume control ........................................................................................................... .....................11 3.3. digital dac volume control ............................................................................................... ..............12 3.4. parametric equalizer ..................................................................................................... ..................12 3.4.1. prescaler & equalizer filter ................... ........................................................................ ....12 3.4.2. eq registers ........................................................................................................... ...........13 3.4.3. equalizer, bass, treble c oefficient & equalizer prescaler ra m .......................................15 3.5. gain and dynamic range control ........................................................................................... ........18 3.6. limiter .................................................................................................................. ............................18 3.7. compressor ............................................................................................................... ......................19 3.7.1. configuration .......................................................................................................... ............20 3.7.2. controlling parameters ................................................................................................. ......20 3.7.3. overview ............................................................................................................... .............21 3.7.4. limiter/compressor registers ..................... ...................................................................... .23 3.7.5. expander registers ..................................................................................................... ......25 3.8. output effects ........................................................................................................... .......................26 3.9. stereo depth (3-d) enhancement ........................................................................................... ........26 3.10. psychoacoustic bass enhancement ..................... .................................................................... .....27 3.11. treble enhancement ...................................................................................................... ...............27 3.12. mute and de-emphasis .................................................................................................... .............28 3.13. mono operation and phase inversion ...................................................................................... .....29 3.13.1. dac control register ................................................................................................. ....29 3.13.2. interpolation and filtering .............. .............. .............. .............. .............. ........... .......... .....30 3.14. analog outputs .......................................................................................................... ....................31 3.14.1. headphone output .............. .............. .............. .............. .............. ........... ........... .......... .....31 3.15. other output capabilities ...... .............. .............. .............. .............. ........... ........... ........... ...............32 3.15.1. audio output control .................................................................................................. .....32 3.15.2. headphone switch .............. .............. .............. .............. .............. ........... ........... .......... .....32 3.15.3. headphone operation ......... .............. .............. .............. .............. ........... ........... ............ ...33 3.15.4. eq operation .......................................................................................................... .........33 4. input audio processing ................................................................................................. 34 4.1. analog inputs ............................................................................................................ .......................34 4.1.1. input registers ........................................................................................................ ...........35 4.2. mono mixing and output config uration ..................................................................................... ......35 4.2.1. adc registers .......................................................................................................... .........36 4.3. microphone bias .......................................................................................................... ....................37 4.3.1. microphone bias control register .....................................................................................37 4.4. programmable gain control ................................................................................................ ............37 4.4.1. input pga softw are control register. ...............................................................................38 4.5. adc digital filter ....................................................................................................... ......................38 4.5.1. adc signal path control re gister .....................................................................................40 4.5.2. adc high pass filter enable modes ............. .............. .............. .............. .............. ............40 4.6. digital adc volume control ............................................................................................... ..............40 4.6.1. adc digital registers .................................................................................................. ......41 4.7. automatic level control (alc) ............................................................................................ ............41 4.7.1. alc operation ......................................................................................................... .........41 4.7.2. alc registers .......................................................................................................... ..........43 4.7.3. peak limiter ........................................................................................................... ............44 4.7.4. input threshold ........................................................................................................ ..........44
3 v0.5 04/11 ?2011 integrated device technology, inc. acs522x01 acs522x01 low-power, high-fidelity, integrated codec 4.8. digital microphone support ............................................................................................... ..............44 4.8.1. dmic register .......................................................................................................... .........47 5. digital audio and control interfaces ................................................................... 48 5.1. data interface ........................................................................................................... .......................48 5.2. master and slave mode operation .......................................................................................... ........48 5.3. audio data formats ....................................................................................................... ..................49 5.4. left justified audio interface ........................................................................................... ................49 5.5. right justified audio interface (assuming n-bit wo rd length) ...........................................................49 5.6. i2s format audio interface ............................................................................................... ...............50 5.7. data interface registers ........................... ...................................................................... .................50 5.7.1. audio data format control register ........... .......................................................................50 5.7.2. audio interface output tri-state ................ ....................................................................... ..51 5.7.3. audio interface bit clock and lr clock config uration ........................................................51 5.7.4. bit clock and lr clock mode selection ........ ....................................................................52 5.7.5. adc output pin state ................................................................................................... .....53 5.7.6. audio interface control 3 register ............ ......................................................................... 53 5.8. bit clock mode ........................................................................................................... ......................53 5.9. control interface ........................................................................................................ ......................54 5.9.1. register write cycle ................................................................................................... .......54 5.9.2. multiple write cycle ................................................................................................... ........55 5.9.3. register read cycle .................................................................................................... ......55 5.9.4. multiple read cycle ...... .............................................................................................. .......56 5.9.5. device addressing and identification .......... .............. .............. ............ ........... ........... .........56 6. audio clock generation ............................................................................................... 58 6.1. internal clock generation (acl k) ......................................................................................... ..........58 6.2. aclk clocking and sample rates ................... ........................................................................ .......58 6.3. dac/adc modulator rate contro l ........................................................................................... ........59 7. characteristics ............................................................................................................ ... 61 7.1. electrical specifications ......................... ....................................................................... ...................61 7.1.1. absolute maximum ratings ............................................................................................... 61 7.1.2. recommended operating conditions ................................................................................61 7.2. device characteristics ................................................................................................... ..................62 7.3. typical power consumption .......................... ...................................................................... ............64 7.4. low power mode power consumpt ion ............. .............. .............. .............. ........... ........... ............ ...64 8. register map ............................................................................................................... ....... 65 9. pinout ..................................................................................................................... .............. 67 9.1. pin tables ............................................................................................................... .........................68 9.1.1. power pins ............................................................................................................. ............68 9.1.2. reference pins ......................................................................................................... .........68 9.1.3. analog input pins ...................................................................................................... .........69 9.1.4. analog output pins ..................................................................................................... .......69 9.1.5. data and control pins .................................................................................................. ......69 9.1.6. clock and no connect pins .............................................................................................. .70 10. package information ................................................................................................... 70 10.1. package diagram .... .............. .............. .............. .............. ........... ........... ........... ............ .................70 11. application information .. .......................................................................................... 71 12. ordering information ................................................................................................. 71 13. disclaimer ................................................................................................................ ......... 71 14. document revision history ....................................................................................... 72
4 v0.5 04/11 ?2011 integrated device technology, inc. acs522x01 acs522x01 low-power, high-fidelity, integrated codec list of figures figure 1. block diagram ....................................................................................................... ............................7 figure 2. output audio processing ............................................................................................. ...................10 figure 3. prescaler & eq filters .............................................................................................. ......................12 figure 4. 6-tap iir equalizer filter .......................................................................................... ......................13 figure 5. dac coefficient ram write sequence .................................................................................. .........15 figure 6. dac coefficient ram read sequence ................................................................................... ........16 figure 7. gain compressor, output vs input .................................................................................... .............19 figure 8. compressor block diagram ...................... ...................................................................... .................21 figure 9. 3-d channel inversion .......................... ..................................................................... .....................26 figure 10. bass enhancement ................................................................................................... ....................27 figure 11. treble enhancement ................................................................................................. ...................28 figure 12. interpolation and filtering ........................................................................................ .....................30 figure 13. input audio processing ............................................................................................. ....................34 figure 14. mic bias ........................................................................................................... .............................37 figure 15. adc filter data path ............................................................................................... ......................38 figure 16. adc input processing ............................................................................................... ....................39 figure 17. alc operation ...................................................................................................... ........................41 figure 18. single digital microphone (dat a is ported to both left and right channels) ............. .............. .........46 figure 19. stereo digital microphone configuration ............................................................................ ..........47 figure 20. master mode ........................................................................................................ .........................48 figure 21. slave mode ......................................................................................................... ..........................48 figure 22. left justified audio interface (assuming n-bit wo rd length) ....... .............. .............. ........... .......... ..49 figure 23. right justified audio interface (assuming n-bi t word length) ....................................................... .49 figure 24. i2s justified audio interface (assuming n-bit wo rd length) ........ .............. .............. ........... .......... ..50 figure 25. bit clock mode ..................................................................................................... .........................54 figure 26. 2-wire serial control interface ............ ........................................................................ ..................55 figure 27. multiple write cycle ......................... ...................................................................... .......................55 figure 28. read cycle ......................................................................................................... ..........................56 figure 29. multiple read cycle ... ............................................................................................. ......................56 figure 30. acss522d01 pinout .................................................................................................. ..................67 figure 31. package drawing .................................................................................................... ......................70
5 v0.5 04/11 ?2011 integrated device technology, inc. acs522x01 acs522x01 low-power, high-fidelity, integrated codec list of tables table 1. power management register 1 .............. .............. .............. .............. .............. ........... ......... ................9 table 2. power management register 2 .............. .............. .............. .............. .............. ........... ......... ................9 table 3. power management register1 -- master clock dis able ............ .............. .............. .............. ............. .9 table 4. dc_coef_sel register ................................................................................................. ................10 table 5. config0 register ..................................................................................................... ......................10 table 6. volume update control regi ster ....................................................................................... ..............11 table 7. gain control register ....................... ......................................................................... .......................11 table 8. dac volume control registers ................. ........................................................................ ...............12 table 9. config1 register ..................................................................................................... ......................13 table 10. daccram read/write regist ers ............ .............. .............. .............. ............ ........... .......... ..........14 table 11. daccram address register .............. .............. .............. .............. .............. ........... ........... ............14 table 12. daccram status register .............. .............. .............. .............. .............. .............. ......... ..............14 table 13. daccram eq addresess ..... .............. .............. .............. .............. .............. ........... .......... .............17 table 14. daccram bass/treble addresse s ............. .............. .............. .............. ........... ............ ......... ........17 table 15. clectl register ........ ............................................................................................. ......................23 table 16. mugain register ................................ ..................................................................... .....................23 table 17. compth register ..................................................................................................... ....................23 table 18. cmprat register ..................................................................................................... .....................23 table 19. catktcl register .................................................................................................... ....................23 table 20. catktch register .................................................................................................... ....................24 table 21. creltcl register .................................................................................................... ....................24 table 22. creltch register .................................................................................................... ....................24 table 23. limth register ...................................................................................................... ........................24 table 24. limtgt register ..................................................................................................... .......................24 table 25. latktcl register .................................................................................................... .....................24 table 26. latktch register .................................................................................................... ....................24 table 27. lreltcl register .................................................................................................... .....................24 table 28. lreltch register .................................................................................................... ....................25 table 29. expth register . .............. .............. .............. .............. ........... ............ ........... ........... .......................25 table 30. exprat register ............ .............. .............. .............. .............. ........... ............ .......... .....................25 table 31. xatktcl register .................................................................................................... .....................25 table 32. xatktch register .................................................................................................... ....................25 table 33. xreltcl register ........ ............................................................................................ .....................25 table 34. xreltch register .................................................................................................... ....................25 table 35. fx control register ................................................................................................. .......................26 table 36. cnvrtr1 register .............................. ...................................................................... ....................29 table 37. hpvol l/r registers ................................................................................................. ...................31 table 38. power management 2 register ......................................................................................... .............32 table 39. additional control register ............ .............. .............. .............. .............. ........... .......... ...................33 table 40. headphone operation ...... .............. .............. .............. .............. .............. ........... .......... ...................33 table 41. eq operation ........................................................................................................ .........................33 table 42. input software control re gister ........ .............. .............. .............. .............. ........... .......... ................35 table 43. inmode register ..................................................................................................... .....................36 table 44. cnvrtr0 register .............................. ...................................................................... ....................36 table 45. aic2 register ....................................................................................................... ..........................36 table 46. power management 1 register - mic bias enabl e ....................................................................... ..37 table 47. invol l&r registers ................................................................................................. ...................38 table 48. cnvrtr0 register .............................. ...................................................................... ....................40 table 49. adc hpf enable ................................. ..................................................................... .....................40 table 50. l/r adc digital volume registers ............ ........................................................................ .............41 table 51. alc control registers ......................... ...................................................................... ....................43 table 52. ngate register ...................................................................................................... ......................44 table 53. dmic clock .......................................................................................................... ..........................45 table 54. valid digital mic configurations ........... ......................................................................... .................46 table 55. dmicctl register .................................................................................................... .....................47 table 56. aic1 register ....................................................................................................... ..........................50 table 57. aic2 register ....................................................................................................... ..........................51 table 58. bit clock and lr clock mode selection ....... .............. .............. ........... ............ ........... .......... ..........52
6 v0.5 04/11 ?2011 integrated device technology, inc. acs522x01 acs522x01 low-power, high-fidelity, integrated codec table 59. adc data output pin state ........................................................................................... .................53 table 60. aic3 register ....................................................................................................... ..........................53 table 61. master mode bclk frequency control register ......................................................................... ..54 table 62. devadrl register ........... .............. .............. .............. .............. ........... ............ .......... .....................56 table 63. devid h&l registers ................................................................................................. ...................57 table 64. revid register ...................................................................................................... ........................57 table 65. reset register ............ .............. .............. .............. .............. ............ ........... ........... .......................57 table 66. adcsr register ...................................................................................................... ......................58 table 67. dacsr register ...................................................................................................... ......................59 table 68. aclk and sample rates ........................ ....................................................................... ................59 table 69. config0 register .................................................................................................... .....................60 table 70. sdm rates ........................................................................................................... ..........................60 table 71. electrical specification: maximum ratings ........................................................................... .........61 table 72. recommended operating conditions .................................................................................... ........61 table 73. device characteristics ......................... ..................................................................... .....................62 table 74. typical power consumption ..................... ...................................................................... ...............64 table 75. low power mode power consumption ............. .............. .............. ........... ........... ............ ......... ........64 table 76. register map ........................................................................................................ ..........................65 table 77. power pins .......................................................................................................... ...........................68 table 78. reference pins ................................. ..................................................................... ........................68 table 79. analog input pins ........ .............. .............. .............. .............. .............. ........... .......... ........................69 table 80. analog output pins .................................................................................................. ......................69 table 81. data and control pins ....................... ........................................................................ .....................69 table 82. clock and no connect pins ........................................................................................... ................70
7 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 1. overview 1.1. block diagram the acs522d01 is an advanced low power codec with integrated headphone amplifiers and pll. to support the design of audio subsystems in a portabl e device, the acs5 22d01 features an intelligent codec architecture with advanced audio processing algorithms, in tegrated with a true cap-less headphone amplifier, and microphone interface with programmable gain. figure 1. block diagram 1.2. audio outputs the acs522d01 provides a line-out/capless stereo headphone port with ground referenced outputs, capable of driving headphones without requiring an external dc blocking capacitor. each endpoint features independent volume controls, including a soft-mute capa bility which can slowly ramp up or down the volume changes to avoid unwanted audio artifacts. the acs522d01 output signal paths consist of digital filters, dacs and output dr ivers. the digital filters and dacs are enabled when the acs522d01 is in ?pla yback only? or ?record and playback? mode. the output drivers can be sepa- rately enabled by individual control bits. the digital filter and audio processing block processe s the data to provide volume control and numerous sound enhancement algorithms. two high performance sigma-delta audio dacs convert the digital data into analog. plls audio processing bass/treble enhancement system eq speaker eq 3-d effect compressor-limiter dynamic range expander source select switch audio processing dac left hp out left hp lin3/dmic_clk* rin1 dacin vol mute adcout anti- pop dac left hp out right hp anti- pop dac right audio processing vol mute mic bias lin1 lin2 d2s + - rin2 rin3/dmic_dat* mux lin1 lin2 mux rin1 rin2 1 bit 1 bit rin1 rin2 mux rin3 d2s lin1 lin2 mux lin3 d2s d2s mux mux s clocking control i2c_scl i2c_sda daclrclk adclrclk dacbclk adcbclk mclk internal audio clock(s) pvdd dvdd_core cpvdd vref agnd + - dvdd_io charge-pump avdd cap+ cap- v- dac right dac dac adcl adcr -97 to +30 db in 0.5 db steps -97 to +30 db in 0.5 db steps digital volume digital volume automatic level control dvss avss cpgnd 2 vref afilt1 afilt2 hp_det test 2 vdd_pll2 vdd_pll1 vss_xtal +0/+10/+20/+30 db boost agc -17 to +30db in 0.75db steps +0/+10/+20/+30 db boost -17 to +30db in 0.75db steps agc vss_pll *digital microphone products
8 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec the digital audio data is converted to oversampled bit streams using 24-bit digital interpolat ion filters, which then enters sigma-delta dacs, and become converted to high quality analog audio signals. to enhance the sound available from the small, low-power speakers typically found in a portable device, the acs522d01 provides nu merous audio enhan cement capabilities. the acs522d0 1 features dual, independent, pro- grammable left/right 6-band equalization, allowing the system designer to provide an advanced system equalizer to accommodate the specific speakers and enclosure design. a compressor/limiter features programmable attack and release thresholds, enabling the system designer to attenuat e loud noise excursions to avoid speaker artifacts, thus allowing the underlying content to be pl ayed at a louder volume without dist ortion. for compressed audio, a program- mable expander is available to help restore the dynamic range of the original content. a stereo depth enhancement algorithm allows common left/right content (e.g. dialog) to be attenuated separately from other content, providing a per- ceived depth separation between background and foregr ound audio. psychoacoustic bass and treble enhancement algorithms achieve a rich, full tone even from originally compressed content, and even with speakers generally unable to play low-frequency sounds. 1.3. audio inputs on the analog input side, the device features multiple line-in/microphone inputs, which can be used for analog micro- phone, or line-in inputs. in addition, digital microphones are also supported. the device provides input gain control, separate volume controls, au tomatic leveling capability, and programmable microphone boost to smooth input record- ing. a programmable silence ?floor? or ?threshol d? can be set to minimize background noise.
9 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 2. power management 2.1. control registers the acs522d01 has control registers to enable system soft ware to control which functions are active. to minimize power consumption, unused func tions should be disabled. to avoid audio artifa cts, it is important to enable or disable functions in the correct order. 2.2. stopping the master clock in order to minimize digital core power consumption, th e master clock may be stopped in standby and off modes by setting the digenb bit (r25, bit 0). note: before digenb can be set, the control bits adcl , adcr, hpl and hpr must be set to zero and a waiting time of 100ms must be observed to allow port ramping/gain fading to complete. any failu re to follow this procedure may cause pops or, if less than 1ms, may prevent the dacs and adcs from re-starting correctly. register address bit label type default description 0x1a power management 1 7bstlrw0 analog in boost left 0 = power down, 1 = power up 6 bstr rw 0 analog in boost right 0 = power down, 1 = power up 5pgalrw0 analog in pga left 0 = power down, 1 = power up 4pgarrw0 analog in pga right 0 = power down, 1 = power up 3 adcl rw 0 adc left 0 = power down,1 = power up 2 adcr rw 0 adc right 0 = power down. 1 = power up 1 micb rw 0 micbias 0 = power down, 1 = power up 0digenbrw0 master clock disable 0: master clock enabled, 1: master clock disabled table 1. power management register 1 register address bit label type default description 0x1b power management 2 7d2srw0 analog in d2s amp 0 = power down, 1 = power up 6hplrw0 lhp output buffer + dac 0 = power down, 1 = power up 5hprrw0 rhp output buffer + dac 0 = power down, 1 = power up 4:3 rsvd rw 0 reserved 2insellrw0 analog in select mux left 0 = power down, 1 = power up 1 inselr rw 0 analog in select mux right 0 = power down, 1 = power up 0vrefrw0 vref (necessary for all other functions) 0 = power down, 1 = power up table 2. power management register 2 register address bit label type default description 0x1a power management 1 0digenbrw0 master clock disable 0 = master clock enabled, 1 = master clock disabled table 3. power management register1 -- master clock disable
10 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3. output audio processing figure 2. output audio processing 3.1. dc removal before processing, a dc removal filter removes the dc co mponent from the incoming audio data. the dc removal fil- ter is programmable. register address bit label type default description r65 (41h) dcofsel 7:3 ? r 0 reserved for future use. 2:0 - rw 5 0: dc_coef = 24'h100000; //2^^-3 = 0.125 1: dc_coef = 24'h040000; 2: dc_coef = 24'h010000; 3: dc_coef = 24'h004000; 4: dc_coef = 24'h001000; 5: dc_coef = 24'h000400; 6: dc_coef = 24'h000100; //2^^-15 = 0.00030517 7: dc_coef = 24'h000040; //2^^-17 table 4. dc_coef_sel register register address bit label type default description r31 (1fh) config0 7:6 asdm[1:0] rw 10h adc modulator rate 5:4 dsdm[1:0] rw 10h dac modulator rate 3:2 rsvd r 0h reserved for future use. 1 dc_bypass rw 0 1 = bypass dc removal filter (warning dc content can damage speakers) 0 rsvd r 0 reserved table 5. config0 register dc removal eq1 eq2 compressor limiter expander prescale 1 prescale 2 gain 33h ? 38h 25h 2dh ? 32h limiter expander control 0 to 46.5 db in 1.5 db steps 3dh ? 3fh 3ah ? 3ch write read 40h address 8ah status daccram 80h ? 96h bass coefficients daccram 97h ? adh treble coefficients phase invert dac volume mute 0 to -95.25db 0.375db steps 18h dacpol 04h ? 05h dac volume dac_l/r 18h mute de- emphasis 18h de-emphasis 39h fxctrl 41h dc-coef_sel daccram 00h ? 3dh eq1 coefficients daccram 40h ? 7dh eq2 coefficients 26h ? 2ch compressor pa bass pa treble 3-d daccram aeh ? afh 3d coefficients daccram afh daccram 96h daccram adh mono mix 18h dmonomix hp out left hp anti- pop dac left hp volume (digital) +6 to -88.5 db in 0.75 db steps 00h audio processing bass/treble enhancement system eq speaker eq 3-d effect compressor-limiter dynamic range expander hp detect interpolation dac_l/r hp out right hp anti- pop dac hp volume (digital) +6 to -88.5 db in 0.75 db steps 01h hp detect right
11 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.2. volume control the signal volume can be controlled digitally, across a gain and attenuation range of -95.25db to 0db (0.375db steps). the level of attenuation is specified by an eight-bit code, ?dacvol_x?, where ?x? is l, or r. the value ?00000000? indi- cates mute; other values select the number of 0. 375db steps above -95.625db for the volume level. the volume update bits control the updating of volume contro l data; when a bit is written as ?0?, the left volume control associated with that bit is updated whenever the left volume register is written and the right volume control is updated when ever the right volume register is written. when a bit is written as ?1?, the left volume data is placed into an internal holding register when the left volume register is written and both the left and right volumes are updated when the right volume register is written. this enables a simultaneous left and right volume update the output path may be muted automatically when a long string of zero data is received. the length of zeros is pro- grammable and a detection flag indicates when a stream of zero data has been detected. register address bit label type default description r10 (0ah) vuctl 7 adcfade rw 1 1 = volume fades between old/new value 0 = volume/mute changes immediately 6 dacfade rw 1 1 = volume fades between old/new value 0 = volume/mute changes immediately 5 rsvd r 0 reserved for future use. 4involurw0 0 = left input volume updated immediately 1 = left input volume held until right input volume register written. 3 adcvolu rw 0 0 = left adc volume updated immediately 1 = left adc volume held until right adc volume register written. 2 dacvolu rw 0 0 = left dac volume updated immediately 1 = left dac volume held until right dac volume register written. 1 rsvd rw 0 reserved 0 hpvolu rw 0 0 = left headphone volume updated immediately 1 = left headphone volume held until right headphone volume register written. table 6. volume update control register register address bit label type default description r33 (21h) gain control (gainctl) 7 zerodet_flag r 0 1 = zero detect length exceeded. 6 rsvd r 0 reserved for future use. 5:4 zerodetlen rw 2 enable mute if input consecutive zeros exceeds this length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples 3 rsvd r 0 reserved for future use. 2 auto_mute rw 1 1 = auto mute if detect long string of zeros on input 1 rsvd r 0 reserved for future use. 0 rsvd r 0 reserved for future use. 7 zerodet_flag r 0 1 = zero detect length exceeded. table 7. gain control register
12 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.3. digital dac volume control the signal volume can be controlled digitally, across a gain and attenuation range of -95.25db to 0db (0.375db steps). the level of attenuation is specified by an eight-bit code, ?dacvol_x?, where ?x? is l, or r. the value ?00000000? indi- cates mute; other values select the number of 0. 375db steps above -95.625db for the volume level. 3.4. parametric equalizer the acs522d01 has a dual 6-band digital parametric equalizer to enable fine tuning of the audio response and prefer- ences for a given system. each eq may be enabled or disabled independently. in all, 186 bytes of memory are required to store the paramete rs for each equalizer: each filter requires 5, 24-bit coeffi- cients. there are 6 filters per channel, requiring a total of 180 bytes of eq coefficient ram. two additional 24-bit values per channel store the prescale value, resulting in 372 bytes to tal, described later. rather than having all 372 bytes be in the i2c address space of the device, access to the eq ram occurs through the control/status registers. 3.4.1. prescaler & equalizer filter the equalizer filter consists of a prescaler and 6 cascaded 6-tap iir filters. the prescaler allows the input to be attenuated prior to the eq filters in case the eq filters introduce gain, and would thus clip if not prescaled. idt provides a tool to enabl e an audio designer to determine appropriate coeffi- cients for the equalizer filters. the filters enable the implementation of a 6-band parametric equalizer with selectable frequency bands, gain, and filter characteristics (high, low, or bandpass). figure 3. prescaler & eq filters the figure below shows the structure of a single eq filter. the a(0) tap is always normalized to be equal to 1 (400000h). the remaining 5 taps are 24-bit twos compliment format programmable coeffi- register address bit label type default description r4 (04h) left dac volume control 7:0 dacvol_l [7:0] rw ff (0db) left dac volume level 0000 0000 = digital mute 0000 0001 = -95.25db 0000 0010 = -94.875db ... 0.375db steps up to 1111 1111 = 0db note: if dacvolu is set, this setting will take effect after the next write to the right input volume register. r5 (05h) right dac volume control 7:0 dacvol_r [7:0] rw ff (0db) right dac digital volume level 0000 0000 = digital mute 0000 0001 = -95.25db 0000 0010 = -94.875db ... 0.375db steps up to 1111 1111 = 0db table 8. dac volume control registers data in eq_prescale eq filter 0 data out eq filter 1 eq filter 2 eq filter 3 eq filter 4 eq filter 5
13 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec cients. (-2 ?? coefficient ? +2). figure 4. 6-tap iir equalizer filter 3.4.2. eq registers ? eq filter enable register register address bit label type default description r32 (20h) config1 7 eq2_en r/w 0 eq bank 2 enable 0 = second eq bypassed, 1 = second eq enabled 6:4 eq2_be[2:0] r/w 0 eq2 band enable. when the eq is enabled the following eq stages are executed. 0 - prescale only 1 - prescale and filter band 0 ... 6 - prescale and filter bands 0 to 5 7 - reserved 3 eq1_en r/w 0 eq bank 1 enable 0 = first eq bypassed, 1 = first eq enabled 2:0 eq1_be[2:0] r/w 0 eq1 band enable. when the eq is enabled the following eq stages are executed. 0 - prescale only 1 - prescale and filter band 0 ... 6 - prescale and filter bands 0 to 5 7 - reserved table 9. config1 register z -1 x(n) b(0) *2 b(1) *2 b(2) z -1 z -1 z -1 y(n) a(1) *2 a(2) z -1 x(n) b(0) b(1) b(2) z -1 z -1 z -1 y(n) a(1) a(2)
14 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec ? daccram read data (0x3d?lo, 0x3e ?mid, 0x3f?hi), daccram write da ta (0x3a?lo, 0x3b?mid, 0x3c?hi) registers these two 24-bit registers provide the 24-bit data holding registers used when doing indire ct writes/reads to the dac coefficient ram. ? daccram address register this 7-bit register provides the address to the internal ra m when doing indirect writes/r eads to the dac coefficient ram. ? daccram status register this control register provides the write/read enable when doing indirect writes/reads to the dac coefficient ram. register address bit label type default description r58 (3ah) daccram_write_lo 7:0 daccrwd[7:0] r/w 0 low byte of a 24-bit data register, contains the values to be written to the daccram. the address written will have been specified by the daccram address fields. r59 (3bh) daccram_write_mid 7:0 daccrwd[15:8] r/w 0 middle byte of a 24-bit data register, contains the values to be written to the daccram. the address written will have been specified by the daccram address fields. r60 (3ch) daccram_write_hi 7:0 daccrwd[23:16] r/w 0 high byte of a 24-bit data register, contains the values to be written to the daccram. the address written will have been specified by the daccram address fields. r61 (3dh) daccram_read_lo 7:0 daccrrd[7:0] r 0 low byte of a 24-bit data register, contains the contents of the most recent daccram address read from the ram. the address read will ha ve been specified by the daccram address fields. r62 (3eh) daccram_read_mid 7:0 daccrrd[15:8] r 0 middle byte of a 24-bit data register, contains the contents of the most recent daccram address read from the ram. the address read will have been specified by the daccram address fields. r63 (3fh) daccram_read_hi 7:0 daccrrd[23:16] r 0 high byte of a 24-bit data register, contains the contents of the most recent daccram address read from the ram. the address read will have been specified by the daccram address fields. table 10. daccram read/write registers register address bit label type default description r64 (40h) daccraddr 7:0 daccradd r/w 0 contains the address (between 0 and 255) of the daccram to be accessed by a read or write. this is not a byte address--it is the address of the 24-bit data item to be access ed from the daccram.this address is automatically incremented after writing to daccram_write_hi or reading from daccram_read_hi (and the 24 bit data from the next ram location is fetched.) table 11. daccram address register register address bit label type default description r138 (8ah) daccrstat 7 daccram_busy r 0 1 = read/write to daccram in progress, cleared by hw when done. 6:0 rsvd r 0 reserved table 12. daccram status register
15 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.4.3. equalizer, bass, treble coefficient & equalizer prescaler ram the dac coefficient ram is a single port 161x24 synchronous ram. it is programmed indirectly through the control bus in the following manner: 1. write target address to daccram_addr register. 2. write d7:0 to the daccram_write_lo register 3. write d15:8 to the da ccram_write_mid register 4. write d23:16 to the daccram_write_hi register 5. on successful receipt of the daccram_write_hi data, the part will automatically start a write cycle. the daccram_busy bit will be set high to indicate that a write is in progress. 6. on completion of the internal write cycle, the daccram_busy bit will be 0 (when op erating the control interface at high speeds - tbd - software must poll this bit to ensure the write cycle is complete before starting another write cycle.) 7. the bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consec- utive eq ram locations. figure 5. dac coefficient ram write sequence reading back a value from the daccram is done in this manner: 1. write target address to daccram_addr register.( eq data is pre-fetched for read even if we don?t use it) 2. start (or repeat start) a write cycle to daccram _read_lo and after the second byte (register address) is acknowledged, go to step 3. (do not complete the write cycle.) 3. signal a repeat start and indicate a read operation 4. read d7:0 (register address incremented after ack by host) 5. read d15:8 (register address incremented after ack by host) 6. read d23:16 (register address incremented and ne xt eq location pre-fetched after ack by host) 7. the host stops the bus cycle to repeat a read cycle for consecutive eq ram locations: 1. start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating daccram_rd_lo as the target address. 2. after the second byte is acknowledged, signal a repeated start. 3. indicate a read operation 4. read the daccram_read_lo regist er as described in step 4 da6 da0 s w a s scl ra1 ra0 a s ra7 rd7 rd0 a s sda register write here writing 1 reigster register write here 28 scl cycles 70 us min. da[6:0], w 2.5 us min. s ra[7:0] rd[7:0] write eq ram address write eq ram write lo write eq ram write mid write eq ram write hi write eq ram write lo eq ram write req = 1 eq ram write must have finished here; eq_a ++ eq ram write lo updated here generic write operation eq ram write operation repeat for multiple consecutive eq ram locations writes eq_a updated; eq ram read req = 1 eq ram read finished; eq read data valid (time not fixed) p s da[6:0], w ra[7:0] rd[7:0] rd[7:0] rd[7:0] s da[6:0], w ra[7:0] rd[7:0] rd[7:0] write eq ram write mid rd7 rd0 a s multiple write cycle rd7 rd0 a s multiple write cycle
16 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5. read the daccram_read_mid regi ster as described in step 5 6. read the daccram_read_hi register as described in step 6 7. repeat steps 8-13 as desired figure 6. dac coefficient ram read sequence ? daccram eq addresess eq 0 eq1 addr channel 0 coefficients addr channel 1 coefficients addr channel 0 coefficients addr channel 1 coefficients 0x00 eq_coef_0f0_b0 0x20 eq_coef_1f0_b0 0x40 eq_coef_2f0_b0 0x60 eq_coef_3f0_b0 0x01 eq_coef_0f0_b1 0x21 eq_coef_1f0_b1 0x41 eq_coef_2f0_b1 0x61 eq_coef_3f0_b1 0x02 eq_coef_0f0_b2 0x22 eq_coef_1f0_b2 0x42 eq_coef_2f0_b2 0x62 eq_coef_3f0_b2 0x03 eq_coef_0f0_a1 0x23 eq_coef_1f0_a1 0x43 eq_coef_2f0_a1 0x63 eq_coef_3f0_a1 0x04 eq_coef_0f0_a2 0x24 eq_coef_1f0_a2 0x44 eq_coef_2f0_a2 0x64 eq_coef_3f0_a2 0x05 eq_coef_0f1_b0 0x25 eq_coef_1f1_b0 0x45 eq_coef_2f1_b0 0x65 eq_coef_3f1_b0 0x06 eq_coef_0f1_b1 0x26 eq_coef_1f1_b1 0x46 eq_coef_2f1_b1 0x66 eq_coef_3f1_b1 0x07 eq_coef_0f1_b2 0x27 eq_coef_1f1_b2 0x47 eq_coef_2f1_b2 0x67 eq_coef_3f1_b2 0x08 eq_coef_0f1_a1 0x28 eq_coef_1f1_a1 0x48 eq_coef_2f1_a1 0x68 eq_coef_3f1_a1 0x09 eq_coef_0f1_a2 0x29 eq_coef_1f1_a2 0x49 eq_coef_2f1_a2 0x69 eq_coef_3f1_a2 0x0a eq_coef_0f2_b0 0x2a eq_coef_1f2_b0 0x4a eq_coef_2f2_b0 0x6a eq_coef_3f2_b0 0x0b eq_coef_0f2_b1 0x2b eq_coef_1f2_b1 0x4b eq_coef_2f2_b1 0x6b eq_coef_3f2_b1 0x0c eq_coef_0f2_b2 0x2c eq_coef_1f2_b2 0x4c eq_coef_2f2_b2 0x6c eq_coef_3f2_b2 0x0d eq_coef_0f2_a1 0x2d eq_coef_1f2_a1 0x4d eq_coef_2f2_a1 0x6d eq_coef_3f2_a1 0x0e eq_coef_0f2_a2 0x2e eq_coef_1f2_a2 0x4e eq_coef_2f2_a2 0x6e eq_coef_3f2_a2 0x0f eq_coef_0f3_b0 0x2f eq_coef_1f3_b0 0x4f eq_coef_2f3_b0 0x6f eq_coef_3f3_b0 0x10 eq_coef_0f3_b1 0x30 eq_coef_1f3_b1 0x50 eq_coef_2f3_b1 0x70 eq_coef_3f3_b1 ra1 da6 a s da0 rd7 s r r a s rd0 a m ra7 1. da: device address 6. a m : acknowledge from master 2. ra: register address 7. n m : not acknowledge from master 3. eq_a: eq ram address 8. s: start 4. rd: register data 9. s r : repeated start 5. a s : acknowledge from slave 10. p: stop scl sda da[6:0], w s ra[7:0] rd[7:0] write eq ram address rd[7:0] read eq ram data lo read eq ram data mid read eq ram data hi eq_a ++; prefetch data da[6:0], r s r rd[7:0] ra[7:0] write eq ram read lo , truncate s p da[6:0], w eq ram data must be valid here generic read operation eq ram read operation eq_a updated; eq ram read req = 1 30 scl cycles 75 us min. repeat for multiple consecutive eq ram locations reads ra0 rd7 rd0 a m rd7 rd0 n m multiple read cycle read 1 register multiple read cycle rd[7:0] s r ra[7:0] write eq ram read lo, truncate s da[6:0], w p rd[7:0] read eq ram data lo da[6:0], r eq ram data must be valid here nack from master to end read cycle
17 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec table 13. daccram eq addresess ? daccram bass/treble addresses 0x11 eq_coef_0f3_b2 0x31 eq_coef_1f3_b2 0x51 eq_coef_2f3_b2 0x71 eq_coef_3f3_b2 0x12 eq_coef_0f3_a1 0x32 eq_coef_1f3_a1 0x52 eq_coef_2f3_a1 0x72 eq_coef_3f3_a1 0x13 eq_coef_0f3_a2 0x33 eq_coef_1f3_a2 0x53 eq_coef_2f3_a2 0x73 eq_coef_3f3_a2 0x14 eq_coef_0f4_b0 0x34 eq_coef_1f4_b0 0x54 eq_coef_2f4_b0 0x74 eq_coef_3f4_b0 0x15 eq_coef_0f4_b1 0x35 eq_coef_1f4_b1 0x55 eq_coef_2f4_b1 0x75 eq_coef_3f4_b1 0x16 eq_coef_0f4_b2 0x36 eq_coef_1f4_b2 0x56 eq_coef_2f4_b2 0x76 eq_coef_3f4_b2 0x17 eq_coef_0f4_a1 0x37 eq_coef_1f4_a1 0x57 eq_coef_2f4_a1 0x77 eq_coef_3f4_a1 0x18 eq_coef_0f4_a2 0x38 eq_coef_1f4_a2 0x58 eq_coef_2f4_a2 0x78 eq_coef_3f4_a2 0x19 eq_coef_0f5_b0 0x39 eq_coef_1f5_b0 0x59 eq_coef_2f5_b0 0x79 eq_coef_3f5_b0 0x1a eq_coef_0f5_b1 0x3a eq_coef_1f5_b1 0x5a eq_coef_2f5_b1 0x7a eq_coef_3f5_b1 0x1b eq_coef_0f5_b2 0x3b eq_coef_1f5_b2 0x5b eq_coef_2f5_b2 0x7b eq_coef_3f5_b2 0x1c eq_coef_0f5_a1 0x3c eq_coef_1f5_a1 0x5c eq_coef_2f5_a1 0x7c eq_coef_3f5_a1 0x1d eq_coef_0f5_a2 0x3d eq_coef_1f5_a2 0x5d eq_coef_2f5_a2 0x7d eq_coef_3f5_a2 0x1e - 0x3e - 0x5e - 0x7e - 0x1f eq_prescale0 0x3f eq_prescale1 0x5f eq_prescale2 0x7f eq_prescale3 addr bass coefficients 1 addr treble coefficients addr 3d coefficients 0x80 bass_coef_ext1_b0 0x97 tr eb_coef_ext1_b0 0xae 3d_coef 0x81 bass_coef_ext1_b1 0x98 tr eb_coef_ext1_b1 0xaf 3d_mix 0x82 bass_coef_ext1_b2 0x 99 treb_coef_ext1_b2 0x83 bass_coef_ext1_a1 0x9a treb_coef_ext1_a1 0x84 bass_coef_ext1_a2 0x9b treb_coef_ext1_a2 0x85 bass_coef_ext2_b0 0x9c treb_coef_ext2_b0 0x86 bass_coef_ext2_b1 0x9d treb_coef_ext2_b1 0x87 bass_coef_ext2_b2 0x9e treb_coef_ext2_b2 0x88 bass_coef_ext2_a1 0x9f treb_coef_ext2_a1 0x89 bass_coef_ext2_a2 0xa0 treb_coef_ext2_a2 0x8a bass_coef_nlf_m1 2 0xa1 treb_coef_nlf_m1 table 14. daccram bass/treble addresses eq 0 eq1 addr channel 0 coefficients addr channel 1 coefficients addr channel 0 coefficients addr channel 1 coefficients
18 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.5. gain and dynamic range control the gain for a given channel is controlled by the dacvol re gisters. the range of gain su pported is from -95.625db to 0db in 0.375db steps. if the result of the gain multiply step w ould result in overflow of the 24-bit output word width, the output is saturated at the max positive or negative value. in addition to simple gain control, the acs522d01 also provides sophisticated dynami c range control. the dynamic range control processing element implements limiting, dynamic range compression, and dynamic range expansion functions. 3.6. limiter the limiter function will lim it the output of the dsp module to the dac modules. if the signal is greater than 0db it will saturate at 0db as the final processing step within the dsp module. there are times when the user may intentionally want the outp ut limiter to perform this sa turation, for example +6db of gain applied within the dsp gain control and then limited to 0db when output to the module would result in a clipped signal driving the speaker output. this clipped signal wo uld obviously contribute to increased distortion on the speaker output which from the user listeni ng perception it would ?sound louder?. at other times, the system implementor may wish to protect speakers from overheating or provide hearing protection by intentionally limiting th e output level before full scale is reached. a limit threshold, independent of the compressor threshold is provided for this purpose. it is expected that th e limit threshold is set to a higher level than the compressor 0x8b bass_coef_nlf_m2 0xa2 treb_coef_nlf_m2 0x8c bass_coef_lmt_b0 0xa3 treb_coef_lmt_b0 0x8d bass_coef_lmt_b1 0xa4 treb_coef_lmt_b1 0x8e bass_coef_lmt_b2 0xa5 treb_coef_lmt_b2 0x8f bass_coef_lmt_a1 0xa6 treb_coef_lmt_a1 0x90 bass_coef_lmt_a2 0xa7 treb_coef_lmt_a2 0x91 bass_coef_cto_b0 0xa8 treb_coef_cto_b0 0x92 bass_coef_cto_b1 0xa9 treb_coef_cto_b1 0x93 bass_coef_cto_b2 0xaa treb_coef_cto_b2 0x94 bass_coef_cto_a1 0xab treb_coef_cto_a1 0x95 bass_coef_cto_a2 0xac treb_coef_cto_a2 0x96 bass_mix 0xad treb_mix 1.all b0 coefficients are set to unit y (400000h) by default. all others, in cluding m1 and m2, are 0 by default. 2.nlf coefficients (m1, m2) have a range defined as +/-8, with 1 sign bit, 3 integer bits, and 20 fraction bits. so, unity for these values is 100000h. this is as opposed to the rest of the coefficient ram, which has a range defined as +/-2, with 1 sign bit, 1 integer bit, and 22 fraction bits. addr bass coefficients 1 addr treble coefficients addr 3d coefficients table 14. daccram bass/treble addresses
19 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec threshold. 3.7. compressor figure 7. gain compressor, output vs input the traditional compressor algorithm pr ovides two functions simultaneously (depending on signal level). for higher level signals, it can provide a compression function to reduce the signal level. for lower le vel signals, it can provide an expansion function for either increa sing dynamic range or noise gating. the compressor monitors the si gnal level and, if the signal is higher than a threshold, will reduce the gain by a pro- grammed ratio to restrict the dynamic range. limiting is an extreme example of the compress or where, as the input sig- nal level is increased, the gain is decrea sed to maintain a specific output level. in addition to limiting the bandwidth of the compressed audi o, it is common for compress ed audio to also compress the dynamic range of the audio. the expansion function in the acs522d01 can help restore the original dynamics to the audio. the expander is a close relative of the compressor. rather than using signal dependent gain to restrict the dynamic range, the expander uses signal dependent gain to expand the dynamic range. thus if a signal level is below a particu- lar threshold, the expander will reduce the gain even further to extend the dynamic range of the material. output (dbfs) input (dbfs) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -16 -18 -20 -22 -14 -12 -10 -8 -6 -4 -2 0 limit threshold: compressor threshold: compressor ratio: 3:1 -14.25 dbfs -6 dbfs expander threshold: -18 dbfs expander ratio: 1:2 expanded output range natural output range compressed output range compressor threshold expander threshold limit threshold
20 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.7.1. configuration this compressor limiter provides th e following configurable parameters. ? compressor ? threshold ? the threshold ab ove which the compressor will re duce the dynamic range of the audio in the compression region. ? ratio ? the ratio between the input dynamic range and the output dynamic range. for example, a ratio of 3 will reduce an input dynamic range of 9db to 3db. ? attack time ? the amount of time that changes in gain are smoothed over during the attack phase of the compressor. ? release time ? the amount of time that changes in gain are smoothed over during the release phase of the compressor. ? makeup gain ? used to increase the overall level of the compressed audio. ? limiter ? threshold ? the threshold ab ove which the limiter will reduce the dynamic range of the audio in the compression region. ? target ? the limit of the output level (t ypically set to the same as threshold). ? attack time ? the amount of time that changes in gain are smoothed over during the attack phase of the limiter. ? release time ? the amount of time that changes in gain are smoothed over during the release phase of the limiter. ? expander ? threshold ? the threshold below which the ex pander will increase the dynamic range of the audio. ? ratio ? the ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. for example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db. ? attack time ? the amount of time that changes in gain are smoothed over during the attack phase of the expander ? release time - the amount of time that changes in gain are smoothed over during the release phase of the expander. ? two level detection algorithms ? rms ? use an rms measurement for the level. ? peak ? use a peak measurement for the level. 3.7.2. controlling parameters in order to control this processing, there are a number of configurable parameters. the parameters and their ranges are: ? compressor/limiter ? threshold ? -40db to 0db relative to full scale. ? ratio ? 1 to 20 ? attack time ? typically 0 to 500ms ? release time ? typically 25ms to 2 seconds ? makeup gain ? 0 to 40db
21 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec ? expander ? threshold ? -30 to -60 db ? ratio ? 1 to 6 ? attack time ? same as above ? release time ? same as above. ? two level detection algorithms ?rms ?peak 3.7.3. overview a basic block diagram of the compressor is shown below: figure 8. compressor block diagram as this diagram shows, there are 3 primary components of the compressor. 1. level detector: the level detector, oddly enough, detects the level of the incoming signal. since the comp/limiter is designed to work on blocks of signals, t he level detector will either find the peak value of the block of samples to be processed or the rms level of the samples within a block. 2. gain calculation: the gain calculation block is responsible for taking the output of the level detector and calculating a target gain based on that level and the compressor and expander thresholds. the compressor recalculates the ta rget gain value every block, typically every 10ms. ? the gain calculation operates in 3 regions: ? linear region ? if the level is higher th an the expander threshold and lower than the compression threshold, then the gain is 1.0 ? compression region ? when the level is higher than the compressor threshold, then the comp/limiter is in the compress ion region. the gain is a function of the compressor ratio and the signal level. ? expansion region ? when the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. in this region, the gain is a function of the signal level and the expansion ratio. ? compression region gain calculation: in the compression region, the gain calculation is: atten(in db) = (1-1/ratio)(threshold(in db) ? level(in db); ? for example, ? ratio = 4:1 compression ? threshold = -16db ? level = -4 db level detector gain calc attack/ release filter peak or rms compare to thresholds calc gain lowpass filter gains based on attack and release audio in audio out
22 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec the required attenuation is: 9db or a gain coefficient of 0.1259. translating this calculation from log space to linear yields the formula: gain =(level/threshold) 1/ratio *(threshold/level) ? expansion region gain calculation: in the ex pansion region, the attenuation calculation is: atten(in db) = (1 - ratio)(threshold-level); ? for example, ? ratio = 3:1 ? threshold = -40db ? level = -44 db the resulting attenuation required is 8db or a gain value of 0.1585. the linear equation for calculating the gain is: gain =(level/threshold) ratio *(threshold/level) ? state transitions: in addition to calculati ng the new gain for the compressor, the gain calcu- lation block will also select the filter coeffi cient for the attack/releas e filter. the rules for selecting the coefficient are as follows: in the compression region: ? if the gain calculated is less than the last gain calculat ed (more compression is being applied), then the filter coeffi cient is the compressor attack. ? if the gain calculated is more than the last ga in calculated (less compression), the filter coef- ficient is the compressor release. ? in the expansion region: ? if the calculated gain is less than the last gain calculated (closing expander, the filter coeffi- cient is the expander attack. ? if the calculated gain is more than the last gain calculated, the filt er coefficient is the expander release. in the linear region: ? modify gain until a gain of 1.0 is obtained. ? if the last non-linear state was compression, use the compressor release. ? if the last non-linear state was ex pansion, use the expander attack. 3. attack/release filter: in order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated by the gain calculation block. in the pc-based comp/limiter, this is achieved using a simple tra cking lowpass filter to smooth out the abrupt tran- sitions. the calculation (using the coefficient (coeff) selected by the gain block) is: filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain; this creates a exponential ramp from the current gain value to the new value.
23 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.7.4. limiter/compressor registers ? general compressor/limiter/expander control ? compressor/limiter/expander make-up gain ? compressor threshold ? compressor ratio register ? compressor attack time constant register (low) register address bit label type default description r37 (25h) clectl 7:5 rsvd r 0h reserved 4 lvl_mode rw 0 cle level detection mode 0 = average 1 = peak 3 windowsel rw 0 window width selection for level detection: 0 = equivalent of 512 samples of selected base rate (~10-16ms) 1 = equivalent of 64 samples of selected base rate (~1.3-2ms) 2 exp_en rw 0 1 = enable expander 1 limit_en rw 0 1 = enable limiter 0 comp_en rw 0 1 = enable compressor table 15. clectl register register address bit label type default description r38 (26h) mugain 7:5 rsvd r 0h reserved 4:0 clemug[4:0] rw 0h 0db..46.5db in 1.5db steps table 16. mugain register register address bit label type default description r39 (27h) compth 7:0 compth[7:0] rw 00h ffh..00h = 0db..95.625db in 0.375db steps. table 17. compth register register address bit label type default description r40 (28h) cmprat 7:5 rsvd r 000 reserved 4:0 cmprat[4:0] rw 00h compressor ratio 00h = reserved 01h = 1.5:1 02h..14h = 2:1..20:1 15h..1fh = reserved table 18. cmprat register register address bit label type default description r41 (29h) catktcl 7:0 catktc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a compressor attack phase. table 19. catktcl register
24 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec ? compressor attack time constant register (high) ? compressor release time constant register (low) ? compressor release time constant register (high) ? limiter threshold register ? limiter target register ? limiter attack time constant register (low ) ? limiter attack time constant register (high ) ? limiter release time constant register (low ) register address bit label type default description r42 (2ah) catktch 7:0 catktc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a compressor attack phase. table 20. catktch register register address bit label type default description r43 (2bh) creltcl 7:0 creltc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a compressor release phase. table 21. creltcl register register address bit label type default description r44 (2ch) creltch 7:0 creltc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a compressor release phase. table 22. creltch register register address bit label type default description r45 (2dh) limth 7:0 limth[7:0] rw 00h ffh..00h = 0db..95.625db in 0.375db steps. table 23. limth register register address bit label type default description r46 (2eh) limtgt 7:0 limtgt[7:0] rw 00h ffh..00h = 0db..95.625db in 0.375db steps. table 24. limtgt register register address bit label type default description r47 (2fh) latktcl 7:0 latktc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a limiter attack phase. table 25. latktcl register register address bit label type default description r48 (30h) latktch 7:0 latktc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a limiter attack phase. table 26. latktch register register address bit label type default description r49 (31h) lreltcl 7:0 lreltc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a limiter release phase. table 27. lreltcl register
25 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec ? limiter release time co nstant register (high ) 3.7.5. expander registers ? expander threshold register ? expander ratio register ? expander attack time constant register (low) ? expander attack time constant register (high) ? expander release time constant register (low) ? expander release time constant register (high) register address bit label type default description r50 (32h) lreltch 7:0 lreltc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a limiter release phase. table 28. lreltch register register address bit label type default description r51 (33h) expth 7:0 expth[7:0] rw 00h expander threshold: 0..95.625 db in 0.375db steps table 29. expth register register address bit label type default description r52 (34h) exprat 7:3 rsvd r 00h reserved exprat[2:0] rw 000 expander ratio 0h..1h = reserved 2h..7h = 1:2..1:7 table 30. exprat register register address bit label type default description r53 (35h) xatktcl 7:0 xatktc[7:0] rw 00h low byte of the time constant used to ramp to a new gain value during a expander attack phase. table 31. xatktcl register register address bit label type default description r54 (36h) xatktch 7:0 xatktc[15:8] rw 00h high byte of the time constant used to ramp to a new gain value during a expander attack phase. table 32. xatktch register register address bit label type default description r55 (37h) xreltcl 7:0 xreltc[7:0] rw 0 low byte of the time constant used to ramp to a new gain value during a expander release phase. table 33. xreltcl register register address bit label type default description r56 (38h) xreltch 7:0 xreltc[15:8] rw 0 high byte of the time constant used to ramp to a new gain value during a expander release phase. table 34. xreltch register
26 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.8. output effects the acs522d01 offers bass enhancement, treble enhanc ement, stereo depth enhancement. the output effects pro- cessing is outlined in t he following sections.l 3.9. stereo depth (3-d) enhancement the acs522d01 has a digital depth enhancement option to ar tificially increase the separation between the left and right channels, by enabling the attenuation of the content co mmon to both channels. the am ount of attenuation is pro- grammable within a range. the input is prescaled (fixed) before summation to prevent saturation. the 3-d enhancement algorithm is a tried an d true algorithm that uses two principles. 1. if the material common to the two channels is removed, then the speakers will sound more 3-d. 2. if the material for the opposite ch annel is presented to the current chan nel inverted, it will tend to cancel any material from the opposite channel on the current ear. for example, if the material from the right is presented to the left ear inverted, it will cancel some of the material from the right ear that is leaking into the right ear. figure 9. 3-d channel inversion note: 3d_mix specifies the amount of the common si gnal that is subtracted from the left and right channels. this number is a fractional amount between 0 and 1. for proper operation, this value is typically negative. register address bit label type default description r57 (39h) fxctl 7:5 rsvd r 000 reserved 43denrw0 3d enhancement enable 0 = disabled 1 = enabled 3 teen rw 0 treble enhancement enable 0 = disabled 1 = enabled 2 tnlfbyp rw 0 treble non-linear function bypass: 0 = enabled 1 = bypassed 1 been rw 0 bass enhancement enable 0 = disabled 1 = enabled 0 bnlfbyp rw 0 bass non-linear function bypass: 0 = enabled 1 = bypassed table 35. fx control register left left right right
27 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.10. psychoacoustic bass enhancement one of the primary aud io quality issues with small spea ker systems is their inability to reproduce signif icant amounts of energy in the bass region (below 200hz). while there is no magic mechanism to make a speaker reproduce frequen- cies that it is not capable of, there ar e mechanisms for fooling the ear into thin king that the bass material is being heard. the psychoacoustic bass processor relies on a psychoacoustic principle called ?missing fundamental?. if the human ear hears a proper series of harmonics for a particular bass note, the listener will hear the fundamental of that series, even if it is not present. a processing algorithm using this principle allows for impr oving the apparent low frequency response of an audio sys- tem below what it is actually capa ble of. below is a diagram of the implementation of this algorithm. . figure 10. bass enhancement this implementation is composed of 5 major components: 1. extract filter ? this filter extracts the bass informatio n that the speaker s ystem can't reproduce. this is a 4th order band pass filter with a typical bandwidth of 1.5 to 2 octaves. 2. nlf ? this is a nonlinear function that is used to generate the harmonics of the fundamentals in the extracted audio. more on this function later. 3. limit filter ? this filter will limit the amplitude of the harmonics gen erated to prev ent the har- monics from creating noise in the midrange. too ma ny harmonics will spill into the mid range and be heard as unwanted buzzing. too few and th e psychoacoustic effect is not reached. the exact composition of this filter is still or be determined. a 2nd order filter is cu rrently sufficient for the nlf function employed. 4. mixing ? this structure allows mixing of the g enerated harmonics and the original material. 5. cutoff filter ? this filter is used to re move all material below the cutoff frequency of the speaker systems. this includes the fundamentals used to create the psychoacoustic effect, since they can't be reproduced. this is a 2nd order high pass filter. 3.11. treble enhancement one of the mechanisms used to limit the bit rate for compre ssed audio is to first remove high frequency information before compression. when these files are decompressed, this can lead to dull sounding audio. the idt treble enhancement replaces these lost high frequencies. nlf extract filter limit filter cutoff filter
28 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec the enhanced treble function works much like the enhanced bass, however it's intended use is different. the enhanced treble uses a non linear function to add treble harmonics to a signal that has limited high-frequency bandwidth (such as a low bit rate mp3). in this case, the algorithm makes use of the audio fact that presence of audio between 4-8k is a good predictor of audio between 10k-20k. figure 11. treble enhancement this implementation extracts the high frequency content that is available in the audio, generates harmonics of those frequencies. these harmonics are then summed back into the original signal, providing a brighter sound. this algorithm has 4 components. ? extract filter ? this filter is used to extract the treble between 4-8k. this is 2 2nd order high pass filters. ? enhanced treble non-linear function ? generates high frequency components ? limit filter ? this filter limits the harmonics generated by the nlf to prevent any significant aliasing. a second order filter is sufficient. ? mixing network ? this simply sums the generated harm onic signals into the original signal. 3.12. mute and de-emphasis the acs522d01 has a soft mute function, which is used to gr adually attenuate the digital signal volume to zero. the gain returns to its previous sett ing if the soft mute is removed. at startup, the codec is muted by default; to enable audio play, the mute bit must be cleared to 0. after the equalization filters, de-emphasis may be performe d on the audio data to compensate for pre-emphasis that may be included in the audio stream. de-emphasis filteri ng is only available for 48khz, 44.1khz, and 32khz sample rates. nlf extract filter limit filter
29 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.13. mono operation and phase inversion normal stereo operation converts left and right channel digi tal audio data to analog in separate dacs. however, it is also possible to have the same signal (left or right) appe ar on both analog output channels by disabling one channel; alternately, there is a mono-mix mode that mixes the two c hannels digitally before converting to analog using only one dac. in this mode, the other dac is switched off, and the resulting mixed stream signal can appear on both analog output channels. the dac ou tput defaults to non-invert ed. setting dacpoll and dacpol r bits will invert the dac output phase on the left and right channels. 3.13.1. dac control register register address bit label type default description r24 (18h) cnvrtr1 7 dacpolr rw 0 invert dac right signal 6 dacpoll rw 0 invert dac left signal 5:4 dmonomix [1:0] rw 00 dac mono mix 00: stereo 01: mono ((l/2)+(r/2)) into dacl, ?0? into dacr 10: mono ((l/2)+(r/2)) into dacr, ?0? into dacl 11: mono ((l/2)+(r/2)) into dacl and dacr 3dacmurw1 digital soft mute 1 = mute 0 = no mute (signal active) 2 deemp rw 0 de-emphasis enable 1 = de-emphasis enabled 0 = no de-emphasis 1:0 rsvd r 00 reserved table 36. cnvrtr1 register
30 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.13.2. interpolation and filtering figure 12. interpolation and filtering input rate = 8/11.024/12khz (qx): 8khz 11.025khz 12khz 16khz 22.05khz 24khz 128khz 176.4khz 192khz 2x from i2s from i2s from i2s from i2s 64khz 88.2khz 96khz 32khz 44.1khz 48khz input rate = 16/22.05/24khz (hx): input rate = 32/44.1/48khz (1x): input rate = 64/88.2/96khz (2x): 256khz 352.8khz 384khz 5.120mhz 7.056mhz 7.680mhz 57t fir-a 11t fir-b 2x 7t fir-c 2x 7t fir-d 2x 24 22 22 22 20 16khz 22.05khz 24khz 2x 64khz 88.2khz 96khz 32khz 44.1khz 48khz 57t fir-a 11t fir-b 2x 7t fir-c 2x 24 22 22 20 128khz 176.4khz 192khz 2x 64khz 88.2khz 96khz 32khz 44.1khz 48khz 57t fir-a 11t fir-b 2x 7t fir-c 2x 24 22 22 128khz 176.4khz 192khz to analog dac sdm 20x 1 20 2x 64khz 88.2khz 96khz 57t fir-a 11t fir-b 2x 24 22 20 128khz 176.4khz 192khz 256khz 352.8khz 384khz to analog dac sdm 20x 1 2.560mhz 3.528mhz 3.840mhz to analog dac sdm 20x 1 to analog dac sdm 20x 1 input rate = 8/11.024/12khz (qx): 8khz 11.025khz 12khz 16khz 22.05khz 24khz 128khz 176.4khz 192khz 2x from i2s from i2s from i2s from i2s 64khz 88.2khz 96khz 32khz 44.1khz 48khz input rate = 16/22.05/24khz (hx): input rate = 32/44.1/48khz (1x): input rate = 64/88.2/96khz (2x): 256khz 352.8khz 384khz 57t fir-a 11t fir-b 2x 7t fir-c 2x 7t fir-d 2x 24 22 22 22 20 16khz 22.05khz 24khz 2x 64khz 88.2khz 96khz 32khz 44.1khz 48khz 57t fir-a 11t fir-b 2x 7t fir-c 2x 24 22 22 20 128khz 176.4khz 192khz 2x 64khz 88.2khz 96khz 32khz 44.1khz 48khz 57t fir-a 11t fir-b 2x 7t fir-c 2x 24 22 22 128khz 176.4khz 192khz to analog dac sdm 20x 1 20 2x 64khz 88.2khz 96khz 57t fir-a 11t fir-b 2x 24 22 20 128khz 176.4khz 192khz 256khz 352.8khz 384khz to analog dac sdm 20x 1 256khz 352.8khz 384khz 7t fir-e 2x 20 to analog dac sdm 20x 1 to analog dac sdm 20x 1 256khz 352.8khz 384khz 7t fir-d 2x 20 input rate = 8/11.024/12khz (qx): 8khz 11.025khz 12khz 16khz 22.05khz 24khz 128khz 176.4khz 192khz 2x from i2s from i2s from i2s from i2s 64khz 88.2khz 96khz 32khz 44.1khz 48khz input rate = 16/22.05/24khz (hx): input rate = 32/44.1/48khz (1x): input rate = 64/88.2/96khz (2x): 57t fir-a 11t fir-b 2x 7t fir-c 2x 7t fir-d 2x 24 22 22 22 20 16khz 22.05khz 24khz 2x 64khz 88.2khz 96khz 32khz 44.1khz 48khz 57t fir-a 11t fir-b 2x 7t fir-c 2x 24 22 22 20 128khz 176.4khz 192khz 2x 64khz 88.2khz 96khz 32khz 44.1khz 48khz 57t fir-a 11t fir-b 2x 24 22 22 128khz 176.4khz 192khz to analog dac sdm 20x 1 2x 64khz 88.2khz 96khz 57t fir-a 24 22 128khz 176.4khz 192khz to analog dac sdm 20x 1 to analog dac sdm 20x 1 to analog dac sdm 20x 1 auto full half 2.560mhz 3.528mhz 3.840mhz 5.120mhz 7.056mhz 7.680mhz 5.120mhz 7.056mhz 7.680mhz 5.120mhz 7.056mhz 7.680mhz 5.120mhz 7.056mhz 7.680mhz 5.120mhz 7.056mhz 7.680mhz 2.560mhz 3.528mhz 3.840mhz 2.560mhz 3.528mhz 3.840mhz 2.560mhz 3.528mhz 3.840mhz 2.560mhz 3.528mhz 3.840mhz
31 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.14. analog outputs 3.14.1. headphone output the hpout pins can drive a 16 ? or 32 ? headphone or alternately drive a line output. the signal vol- ume of the headphone amplifier can be independently adjusted under software control by writing to hpvol_l and hpvol_r. setting th e volume to 0000000 will mute the output driver; the output remains at ground, so that no click noise is produced when muting or un-muting. gains above 0db run the risk of clipping large signals. to minimize artifacts such as clicks and zipper noise, the headphone out puts feature a volume fade function that smoothly changes volume from the current value to the target value. 3.14.1.1. headphone volume control registers register address bit label type default description r2 (00h) hpvoll 7 rsvd r 0 reserved 6:0 hpvol_l [6:0] rw 1110111 (0db) left headphone volume 1111111 = +6db 1111110 = +5.25db ? 1110111 = 0db ... 0000001 = -88.5db 0000000 = analog mute note: if hpvolu is set, this setting will take effect after the next write to the right input volume register. r3 (01h) hpvolr 7 rsvd r 0 reserved 6:0 hpvol_r [6:0] rw 1110111 right headphone volume 1111111 = +6db 1111110 = +5.25db ? 1110111 = 0db ... 0000001 = -88.5db 0000000 = analog mute table 37. hpvol l/r registers
32 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.15. other output capabilities each audio analog output can be separately enabled. disa bling outputs serves to reduce power consumption, and is the default state of the device. 3.15.1. audio output control see power management section. th e output enable bits are also power management bits and the outputs will be turned off when disabled. 3.15.2. headphone switch the hpdetect pin is used to detect connecti on of a headphone. when headphone insertion is detected, the codec can automatically disable/enable the headphone outputs. control bits determine the meaning and polarity of the input. in addition to enabling and disabling outputs, the eq may also be controlled using the hp_det pin. the 2 eq filters may be configured so that one eq is active when the headphone output is active and the other eq is active when the speaker ou tput is active (independent hp and speaker eq). one eq may be enabled only when the speaker is active and the other eq may be on when either of the outputs are active (speaker compensation an d user eq) or other combinations are possible. note that the eq coefficients must be programmed and the eqs must be enabled using their control registers. the hp_det logic can only disable the eq filters. register address bit label type default description r27 (1bh) power management (2) 7 d2s rw 0 analog in d2s amp enable 6 hpoutl rw 0 left headphone output enable 5 hpoutr rw 0 right headphone output enable 4 rsvd rw 0 reserved 3 rsvd rw 0 reserved 2 insell rw 0 analog in se lect mux left enable 1 inselr rw 0 analog in select mux right enable 0 vref rw 1 voltage reference note : a value of ?1? indicates the output is enabled; a value of ?0? disables the output. table 38. power management 2 register
33 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 3.15.2.1. headphone switch register 3.15.3. headphone operation 3.15.4. eq operation register address bit label type default description r29 (1ch) additional control (ctl) 7hpswenrw0 headphone switch enable 0: headphone switch disabled 1: headphone switch enabled 6 hpswpol rw 0 headphone switch polarity 0: hpdetect high = headphone 1: hpdetect high = reserved 5:4 eq2sw[1:0] rw 00 eq2 behavior due to headphone output state 3:2 eq1sw[1:0] rw 00 eq1 behavior due to headphone output state 1 rsvd rw 0 reserved 0toenrw0 zero cross time-out enable 0: time-out disabled 1: time-out enabled - volumes updated if no zero cross event has occurred before time-out table 39. additional control register hpswen hpswpol hp_det pin state hpout 1 1.hpout = logical or of the hpl and hpr enable (power state) bits headphone enabled 0xx0no 0xx0no 0xx1yes 0xx1yes 100xno 100xno 1010no 1011yes 1100no 1101yes 111xno 111xno table 40. headphone operation eqnsw1 eqnsw0 eq behavior 1 1.eq must be enabled. eq behavior is dependent on hp_det and output power state programming. 0 0 eq is not disabled due to headphone logic 0 1 eq is disabled when headphone output is active 10reserved 11reserved table 41. eq operation
34 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4. input audio processing figure 13. input audio processing 4.1. analog inputs the acs522d01 provides multiple high impedance, low capacitance ac-coupled analog inputs with an input signal path to the stereo adcs. prior to the ad c, there is a multiplexor that allows th e system to select wh ich input is in use. following the mux, there is a programmable gain amplifier and also an optional microphone gain boost. the gain of the pga can be controlled either by the system, or by th e on-chip level contro l function. the stereo record path can also operate with the two channels mixed to mono either in the analog or digital domains. signal inputs are biased internally to avss but ac coupling capacitors are required when connecting microphones (due to the 2.5v microphone bias) or when offsets woul d cause unacceptable ?zipper noise? or pops when changing pga or boost gain settings. to avoid audio artifacts, the line inputs are kept biased to analog ground when they are muted or the device is placed into standby mode. vol mute vol mute mic bias d2s + - mux lin1 lin2 mux rin1 rin2 1 bit 1 bit rin1 rin2 mux rin3 d2s lin1 lin2 mux lin3 d2s d2s mux mux s vref agnd + - adcl adcr -17.25 to +30db in 0.75db steps -17.25 to +30db in 0.75db steps -71.25 to +24 db in 0.375 db steps -71.25 to +24 db in 0.375 db steps automatic level control 18h mono mix 0dh right input select 0ch left input select 14h adc data select 1ah mic bias 08h left input volume 09h right input volume zero cross detect 08h 09h 16h hpf enable 16h adc polarity 07h adc right digital volume 06h adc leftt digital volume 0fh alc control 1 10h alc control 2 11h alc control 3 12h noise gate control 1ah adc power management adc output configuration hpf hpf src src 0eh alc control 0 0bh d2s input select +0/+10/+20/+30 db 0ch left boost boost pga +0/+10/+20/+30 db boost 0dh right boost pga
35 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.1.1. input registers 4.2. mono mixing and ou tput configuration the stereo adc can operate as a stereo or mono device, or the two channels can be mixed to mono. mixing can occur either in the input path (analog, before adc) or afte r the adc. monomix determines whether to mix to mono, and where. for analog mono mix, either the left or right channel ad c can be used for the audio stream. the other adc may be powered off to conserve power. a differential input amplifie r may be selected as a mono source to either adc input. this d2s amplifier can select either input 1 or input 2 using the ds bit. the system also has the flexibility to se lect the data output. adcds el configures the interfac e, assigning the source of the left and right adc independently. register address bit label type default description r12 (0ch) adc signal path control left (insell) 7:6 insel_l rw 00 left channel input select 00 = linput1 01 = linput2 10 = linput3 11 = d2s 5:4 micbst_l rw 00 left channel microphone gain boost 00 = boost off (bypassed) 01 = 10db boost 10 = 20db boost 11 = 30db boost 3:0 rsvd r 0000 reserved r13 (0dh) adc signal path control right (inselr) 7:6 insel_r rw 00 right channel input select 00 = rinput1 01 = rinput2 10 = rinput3 11 = d2s 5:4 micbst_r rw 00 right channel microphone gain boost 00 = boost off (bypassed) 01 = 10db boost 10 = 20db boost 11 = 30db boost 3:0 rsvd r 0000 reserved table 42. input software control register
36 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.2.1. adc registers 4.2.1.1. adc d2s input mode register 4.2.1.2. adc mono, filter and inversion register 4.2.1.3. adc data output configuration register register address bit label type default description r11 (0bh) adc input mode (inmode) 7:1 rsvd r 0h reserved 0dsrw0 differential input select 0: lin1 - rin1 1: lin2 - rin2 table 43. inmode register register address bit label type default description r22 (16h) adc control (cnvrtr0) 7 adcpolr rw 0 adc right channel polarity 0 = normal 1 = inverted 6adcpollrw0 adc left channel polarity 0 = normal 1 = inverted 5:4 amonomix [1:0] rw 00 adc mono mix 00: stereo 01: analog mono mix (using left adc) 10: analog mono mix (using right adc) 11: digital mono mix (adcl/2 + adcr/2 on both left and right adc outputs) 3 adcmu rw 1 1 = mute adc 2hporrw0 high pass offset result 0 = discard offset when hpf disabled 1 = store and use last ca lculated offset when hpf disabled 1 adchpdr rw 0 adc high pass filter disable (right) 0 adchpdl rw 0 adc high pass filter disable (right) table 44. cnvrtr0 register register address bit label type default description r20 (14h) audio interface control 2 (aic2) 7:6 dacdsel[1:0] rw 00 00: left dac = left i2s data; right dac = right i2s data 01: left dac = left i2s data; right dac = left i2s data 10: left dac = right i2s data; right dac = right i2s data 11: left dac = right i2s data; right dac = left i2s data 5:4 adcdsel[1:0] rw 00 00: left i2s data = left a dc; right i2s data = right adc 01: left i2s data = left a dc; right i2s data = left adc 10: left i2s data = right adc; right i2s data = right adc 11: left i2s data = right adc; right i2s data = left adc 3 tri rw 0 interface tri-state (see section 9.2.4) 2:0 blrcm rw 0 bitclock and lrclock mode (see section 9.2.4) table 45. aic2 register
37 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.3. microphone bias the micbias output is used to bias el ectric type microphones. it provides a low noise reference voltage used for an external resistor biasing network. the micb control bit is used to enable the output. the micbias can source up to 3ma of current; therefore, the external resistors must be large enough to conform to this limit. 4.3.1. microphone bias control register figure 14. mic bias 4.4. programmable gain control the programmable gain amplif ier (pga) enables the input si gnal level to be matched to the adc input range. ampli- fier gain is adjustable across the range +30db to ?17.25d b (using 0.75db steps). the pga can be controlled directly by the system software using the input volume control regi sters (involl and involr), or alternately the automatic level control (alc) function can automatic ally control the gain. if the alc functi on is used, writing to the input volume control registers has no effect. left and right input gains ar e independently adjustabl e. by controlling the update bit (i nvolu), the left and right gain settings can be simultaneously updated. to eliminate zipper noise, lzcen and rzcen bits enable a zero-cross detec- tor to insure changes only occur when the signal is at ze ro. a time-out for zero-cross is also provided, using toen in register r29 (1dh). software can also mute the inputs in the analog domain. register address bit label type default description r26 (1ah) power management (1) 1micbrw0 microphone bias enable 0 = off (high impedance output) 1 = on table 46. power management 1 register - mic bias enable + - internal mic voltage micbias 2.5v micb internal resistor agnd internal resistor
38 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.4.1. input pga software control register. 4.5. adc digital filter to provide the correct sampling frequency on the digital audio outputs, adc filters perform true 24-bit signal processing and convert the raw mu lti-bit oversampled da ta from the adc using the digita l filter path illustrated below. figure 15. adc filter data path register address bit label type default description r8 (08h) left input volume (involl) 7rsvdrw0 6izclrw0 left channel zero cross detector 1 = change gain on zero cross only 0 = change gain immediately note: if involu is set, this setting will take effect after the next write to the right input volume register. 5:0 invol_l [5:0] rw 010111 (0db) left channel input volume control 111111 = +30db 111110 = +29.25db .. 0.75db steps down to 000000 = -17.25db note: if involu is set, this setting will take effect after the next write to the right input volume register. r9 (09h) right input volume (involr) 7rsvdrw0 6izcrrw0 right channel zero cross detector 1 = change gain on zero cross only 0 = change gain immediately 5:0 invol_r [5:0] rw 010111 (0db) right channel input volume control 111111 = +30db 111110 = +29.25db .. 0.75db steps down to 000000 = -17.25db r28 (1ch) additional control (ctl) 0toenrw0 zero cross time-out enable 0: time-out disabled 1: time-out enabled - volumes updated if no zero cross event has occurred before time-out table 47. invol l&r registers
39 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec figure 16. adc input processing the adc digital filters contain a software-selectable digital hi gh pass filter. when the high-pass filter is enabled, the dc offset is continuously calculated and su btracted from the input signal. the hpor bit enables the last calculated dc off- set value to be stored when the high-pass f ilter is disabled; this value will then c ontinue to be subtra cted from the input signal. to provide support fo r calibration, the stored and subtracted value will not change unless t he high-pass filter is enabled even if the dc value is changed . the high pass filter may be enabled se parately for each of the left and right channels. the output data format can be programmed by the system. this allows stereo or mono recording streams at both inputs. software can change the polarity of the output signal. output rate = 8/11.025/12khz (qx): 8khz 11.025khz 12khz output rate = 16/22.05/24khz (hx): output rate = 32/44.1/48khz (1x): output rate = 64/88.2/96khz (2x): 128khz 176.4khz 192khz 128khz 176.4khz 192khz 64khz 88.2khz 96khz 64khz 88.2khz 96khz 64khz 88.2khz 96khz 32khz 44.1khz 48khz 16khz 22.05khz 24khz 1 from analog adc cic 1/80x 1 5.120mhz 7.056mhz 7.68mhz from analog adc cic 1/80x 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 10.240mhz 14.112mhz 15.360mhz 7t fir-c 11t fir-b 57t fir-a 17 1/2x 1/2x 22 22 1/2x 24 to i2s 16khz 22.05khz 24khz 32khz 44.1khz 48khz 64khz 88.2khz 96khz 11t fir-b 57t fir-a 1/2x 17 22 1/2x 24 to i2s 57t fir-a 17 1/2x 24 to i2s 32khz 44.1khz 48khz 11t fir-b 57t fir-a 1/2x 17 22 1/2x 24 to i2s output rate = 8/11.025/12khz (qx): 8khz 11.025khz 12khz output rate = 16/22.05/24khz (hx): output rate = 32/44.1/48khz (1x): output rate = 64/88.2/96khz (2x): 128khz 176.4khz 192khz 128khz 176.4khz 192khz 64khz 88.2khz 96khz 64khz 88.2khz 96khz 64khz 88.2khz 96khz 32khz 44.1khz 48khz 16khz 22.05khz 24khz 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 7t fir-c 11t fir-b 57t fir-a 17 1/2x 1/2x 22 22 1/2x 24 to i2s 16khz 22.05khz 24khz 32khz 44.1khz 48khz 64khz 88.2khz 96khz 11t fir-b 57t fir-a 1/2x 17 22 1/2x 24 to i2s 57t fir-a 17 1/2x 24 to i2s 32khz 44.1khz 48khz 11t fir-b 57t fir-a 1/2x 17 22 1/2x 24 to i2s auto full output rate = 8/11.025/12khz (qx): 8khz 11.025khz 12khz output rate = 16/22.05/24khz (hx): output rate = 32/44.1/48khz (1x): output rate = 64/88.2/96khz (2x): 64khz 88.2khz 96khz 64khz 88.2khz 96khz 64khz 88.2khz 96khz 32khz 44.1khz 48khz 16khz 22.05khz 24khz 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 1 from analog adc cic 1/80x 7t fir-c 11t fir-b 57t fir-a 17 1/2x 1/2x 22 22 1/2x 24 to i2s 16khz 22.05khz 24khz 32khz 44.1khz 48khz 64khz 88.2khz 96khz 11t fir-b 57t fir-a 1/2x 17 22 1/2x 24 to i2s 17 to i2s 32khz 44.1khz 48khz 57t fir-a 17 1/2x 24 to i2s half 7t fir-c 1/2x 22 7t fir-d 1/2x 22 128khz 176.4khz 192khz 128khz 176.4khz 192khz 10.240mhz 14.112mhz 15.360mhz 5.120mhz 7.056mhz 7.68mhz 5.120mhz 7.056mhz 7.68mhz 5.120mhz 7.056mhz 7.68mhz 5.120mhz 7.056mhz 7.68mhz 5.120mhz 7.056mhz 7.68mhz 10.240mhz 14.112mhz 15.360mhz 10.240mhz 14.112mhz 15.360mhz 10.240mhz 14.112mhz 15.360mhz 10.240mhz 14.112mhz 15.360mhz
40 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.5.1. adc signal path control register 4.5.2. adc high pass filter enable modes 4.6. digital adc volume control the adc volume can be controlled digitally, across a gain and attenuation range of -71.25db to +24db (0.375db steps). the level of attenuation is specified by an eigh t-bit code ?adcvol_x?, where ?x? is l, or r. the value ?00000000? indicates mute; other values describe the number of 0.375db steps above -71.25db. the adcvolu bit controls the updating of digital volume co ntrol data. when adcvolu is written as ?0?, the adc digi- tal volume is immediately updated with the adcvol_l data when the left adc digital vo lume register is written. when adcvolu is set to ?1?, the adcvol _l data is held in an internal holding register until the right adc digital vol- ume register is written. register address bit label type default description r22 (16h) adc control (cnvrtr0) 7 adcpolr rw 0 0 = right polarity not inverted 1 = right polarity inverted 6adcpollrw0 0 = left polarity not inverted 1 = left polarity inverted 5:4 amonomix [1:0] rw 00 adc mono mix 00: stereo 01: analog mono mix (using left adc) 10: analog mono mix (using right adc) 11: digital mono mix 3 adcmu rw 1 1 = mute adc 2hporrw0 high pass offset result 0 = discard offset when hpf disabled 1 = store and use last calculated offset when hpf disabled 1 adchpdr rw 0 adc high pass filter disable (right) 0 adchpdl rw 0 adc high pass filter disable (right) table 48. cnvrtr0 register adchpdr adchpdl high pass mode 0 0 high-pass filter enabled on left and right channels 0 1 high-pass filter disabled on left channel, enabled on right channel 1 0 high-pass filter enabled on left channel, disabled on right channel 1 1 high-pass filter disabled on left and right channels table 49. adc hpf enable
41 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.6.1. adc digital registers 4.7. automatic level control (alc) the acs522d01 has an automatic level control to achieve re cording volume across a range of input signal levels. the device uses a digital peak detector to monitor and adjusts the pga gain to provide a signal level at the adc input. a range of adjustment between ?6db and ?28.5db (relative to adc full scale) can be selected. the device provides pro- grammable attack, hold, and decay times to smooth adjustment s. the level control also feat ures a peak limiter to pre- vent clipping when the adc input exceeds a threshold. note th at if the alc is enabled, t he input volume controls are ignored. 4.7.1. alc operation figure 17. alc operation when alc is enabled, the recording volume target can be programmed between ?6db and ?28.5db (relative to adc full scale). the alc will attempt to keep the ad c input level to within +/-0.5db of the target level. an upper limit for the pga gain can also be imposed, using the maxgain control bits. register address bit label type default description r6 (06h) left adc digital volume 7:0 adcvol_l [7:0] rw 10111111 (0db) left adc digital volume control 0000 0000 = digital mute 0000 0001 = -71.25db 0000 0010 = -70.875db ... 0.375db steps up to 1111 1111 = +24db note: if adcvolu is set, this setting will take effect after the next write to the right input volume register. r7 (07h) right adc digital volume 7:0 adcvol_r [7:0] rw 10111111 (0db) right adc digital volume control 0000 0000 = digital mute 0000 0001 = -71.25db 0000 0010 = -70.875db ... 0.375db steps up to 1111 1111 = +24db table 50. l/r adc digital volume registers
42 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec hold time specifies the delay between detecting a peak level being below target, and the pga gain beginning to ramp up. it is specified as 2 n *2.67ms, enabling a range between 0ms and over 40s.; ramp-down begins immediately if the signal level is above the target. decay (gain ramp-up) time is the time that it takes for the pga to ramp up across 90% of its range. the time is 2 n *24ms. the time required for the recording level to return to its target value therefore depends on the decay time and on the gain adjustment required. attack (gain ramp-down) time is the time that it takes for the pga to ramp down across 90% of its range. time is specified as 2 n *24ms. the time required for the recording level to return to its target value depends on both the attack time and on the gain adjustment required. when operating in stereo, the peak detector takes the maximum of left and right channel peak val- ues, and both pgas use the same gain setting, to preserve the stereo image. if the alc function is only enabled on one channel, only one pga is controlled by the alc mechanism, and the other channel runs independently using the pga gain set through the control registers. if one adc channel is unus ed, the peak detector will ignore that channel. the alc function can operate when the two adc outputs are mixed to mono in the digital domain or in the analog domain.
43 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.7.2. alc registers register address bit label type default description r14 (0eh) alc control 0 7:3 rsvd r 00000 reserved 2 alc mode rw 0 0: alc mode 1: limiter mode 1:0 alcsel [1:0] rw 00 (off) alc function select 00 = alc off (pga gain set by register) 01 = right channel only 10 = left channel only 11 = stereo (pga registers unused) note: ensure that linvol and rinvol settings (reg. 0 and 1) are the same before entering this mode. r15 (0fh) alc control 1 7rsvd r0reserved 6:4 maxgain [2:0] rw 111 (+30db) set maximum gain of pga 111: +30db 110: +24db ?.(-6db steps) 001: -6db 000: -12db 3:0 alcl [3:0] rw 1011 (-12db) alc target ? sets signal level at adc input 0000 = -28.5db fs 0001 = -27.0db fs ? (1.5db steps) 1110 = -7.5db fs 1111 = -6db fs r16 (10h) alc control 2 7rsvdrw0 6:4 mingain rw 000 sets the minimum gain of the pga 000 = -17.25db 001 = -11.25 ... 110 = +18.75db 111 = +24.75db where each value represents a 6db step. 3:0 hld [3:0] rw 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s r17 (11h) alc control 3 7:4 dcy [3:0] rw 0011 (192ms) alc decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ? (time doubles with every step) 1010 or higher = 24.58s 3:0 atk [3:0] rw 0010 (24ms) alc attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ? (time doubles with every step) 1010 or higher = 6.14s table 51. alc control registers
44 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 4.7.3. peak limiter to prevent clipping, the alc circuit also includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), th e pga gain is ramped down at the maximum attack rate, until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. 4.7.4. input threshold to avoid hissing during quiet periods, the acs522d01 has an input threshold noise gate function that compares the signal level at the inputs to a noise gate threshold. below the threshold, the pro- grammable gain can be held , or the adc output can be muted. the threshold can be adjusted in increments of 1.5db. the noise gate activates when the signal-level at the input pin is less than the noise gate threshold (ngth) setting. the adc output can be muted. alternatively, the pga gain can be held . the threshold is adjusted in 1.5db steps. the noise gate only works in conjunction with the alc, and always operates on the same channel(s) as the alc. 4.7.4.1. noise gate control register 4.8. digital microphone support line input 3 may be an analog line (mic) or digital microphone input depending on the part option. the digital microphone interface permits connection of a digital microphone(s) to the codec via the dmic_dat, and dmic_clk 2-pin interface. dmic_dat is an input that ca rries individual channels of digital microphone data to the adc. in the event that a single microphone is used, the data is ported to both adc channels. this mode is selected using a control bit and the left time slot is copied to the adc left and right inputs. the dmic_clk output is synchronous to the internal master (dsp) clock and is adjustable in 4 steps. each step pro- vides a clock that is a multiple of the chosen adc base ra te and modulator rate.the default frequency is 320/3 times the adc base rate for 32khz, and 80 times the base rate for 44.1khz and 48khz base rates. register address bit label type default description r12 (12h) noise gate control (ngate) 7:3 ngth [4:0] rw 00000 noise gate threshold (compared to adc full-scale range) 00000 -76.5dbfs 00001 -75dbfs ? 1.5 db steps 11110 -31.5dbfs 11111 -30dbfs 2:1 ngg [1:0] rw 00 noise gate type x0 = pga gain held 01 = mute adc output 11 = reserved (do not use this setting) 0ngatrw0 noise gate function enable 1 = enable 0 = disable table 52. ngate register
45 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec the two dmic data inputs are shown connected to the a dcs through the same multiplexors as the analog ports. although the internal implementation is different between t he analog ports and the digital microphones, the functionality is the same. in most ca ses, the default values for the dmic clock ra te and data sample phas e will be appropriate and an audio driver will be able to co nfigure and use the digital microphon es exactly like an analog microphone. if the adc path is powered down, the dmic _clk output will be driven low to pl ace the dmic element into a low power state. (many digital microphones will enter a low power state if the clock input is held at a dc level or toggled at a slow rate.) sdm rate dmrate [1:0] base rate dspclk dmic_clk divisor dmic_clk full 00 32 khz 40.960 mhz 12 3.413333 mhz 44.1 khz 56.448 mhz 16 3.528 mhz 48 khz 61.440 mhz 16 3.84 mhz 01 32 khz 40.960 mhz 16 2.56 mhz 44.1 khz 56.448 mhz 20 2.8224 mhz 48 khz 61.440 mhz 20 3.072 mhz 10 32 khz 40.960 mhz 20 2.048 mhz 44.1 khz 56.448 mhz 24 2.352 mhz 48 khz 61.440 mhz 24 2.56 mhz 11 32 khz 40.960 mhz 24 1.706667 mhz 44.1 khz 56.448 mhz 32 1.764 mhz 48 khz 61.440 mhz 32 1.92 mhz half 00 32 khz 40.960 mhz 16 2.56 mhz 44.1 khz 56.448 mhz 16 3.528 mhz 48 khz 61.440 mhz 16 3.84 mhz 01 32 khz 40.960 mhz 24 1.706667 mhz 44.1 khz 56.448 mhz 24 2.352 mhz 48 khz 61.440 mhz 24 2.56 mhz 10 32 khz 40.960 mhz 32 1.28 mhz 44.1 khz 56.448 mhz 32 1.764 mhz 48 khz 61.440 mhz 32 1.92 mhz 11 32 khz 40.960 mhz 40 1.024 mhz 44.1 khz 56.448 mhz 40 1.4112 mhz 48 khz 61.440 mhz 40 1.536 mhz table 53. dmic clock
46 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec the codec supports the following di gital microphone configurations: figure 18. single digital microphone (data is ported to both left and right channels) digital mics data sample notes 0 n/a no digital microphones 1 single edge when using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone for ?left? and select mono operation. ?left? d-mic data is used for adc left and right channels. 2 double edge external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digital microphones that don?t support alternative clock edge (multiplexed output) capability. table 54. valid digital mic configurations dmic_dat dmic_clk right channel left channel valid data valid data valid data dmic_dat dmic_clk single line in pin on-chip multiplexer pin digital microphone on-chip off-chip mux stereo channels output stereo adc pcm dmic_dat dmic_clk left & right channel valid data valid data valid data valid data single ?left? microphone, dmic input set to mono input mode. single microphone not suppo rting multiplexed output.
47 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec figure 19. stereo digital microphone configuration 4.8.1. dmic register register address bit label type default description r36 (24h) d-mic control (dmicctl) 7 dmicen rw 0 digital microphone enable 0 = dmic interface is disabled (dmic_clk low, dmic muted) 1 = dmic interface is enabled 6:5 rsvd r 00 reserved 4dmonorw0 0 = stereo operation, 1 = mono operation (left channel duplicated on right) 3:2 dmphadj[1:0] rw 00 selects when the d-mic data is latched relative to the dmic_clk. 00 = left data rising edge / right data falling edge 01 = left data center of high / right data center of low 10 = left data falling edge / right data rising edge 11 = left data center of low / right data center of high 1:0 dmrate[1:0] rw 00 selects the dmic clock rate: see table in text table 55. dmicctl register dmic_dat dmic_clk right channel left channel valid data r valid data l valid data r valid data l valid data r digital microphones dmic_clk mux stereo channels output pin pin external multiplexer on-chip multiplexer on-chip off-chip stereo adc pcm mux dmic_dat
48 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5. digital audio and control interfaces 5.1. data interface for digital audio data, the acs522d01 uses five pins to input and output digital audio data. ? adcdout: adc data output ? adclrck: adc data alignment clock ? adcbclk: bit clock, for synchronization ? dacdin: dac data input ? daclrck: dac data alignment clock ? dacbclk: bit clock, for synchronization the clock signals adcbclk, adclrck, dacbclk, and daclrck are outputs when the acs522d01 operates as a master; they are inputs when it is a slave. three different data formats are supported: ? left justified ? right justified ?i 2 s all of these modes are msb first. 5.2. master and slave mode operation the acs522d01 can be used as either a ma ster or slave device, selected by th e ms bit. when operating as a master, the acs522d01 generates adcbclk, adclrclk, dacbclk and daclrclk and controls sequencing of the data transfer the data pins. in slave mode, the acs522d01 provides data aligned to clocks it receives. figure 20. master mode figure 21. slave mode adcbclk adclrclk adcdout dacbclk daclrclk dacdin codec dsp encoder/ decoder adcbclk adclrclk adcdout dacbclk daclrclk dacdin codec dsp encoder/ decoder
49 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5.3. audio data formats the acs522d01 supports 3 common audio interface formats and programmable clocking that provides broad compat- ibility with dsps, consumer audio and video socs, fp gas, handset chipsets, a nd many other products. in all modes, depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. if the co nverter word length is smaller than the number of clocks per sample in the frame then the dac will ignore (truncate) the extra bits while the adc will zero pad the ou tput data. if the co nverter word length chosen is larger than the numb er of clocks available per sample in the fr ame, the adc data will be truncated to fit the frame and the dac data will be zero padded. 5.4. left justified audio interface in left justified mode, the msb is available on the first risi ng edge of bclk following a lrclk transition. the other bits are then transmitted in order. the lrclk signal is high when left channel data is present and low when right channel data is present. figure 22. left justified audio interface (assuming n-bit word length) 5.5. right justified audio interf ace (assuming n-bit word length) in right justified mode, the lsb is available on the last rising edge of bclk before a lrclk transition. all other bits are transmitted in order. the lrclk signal is high when left channel data is present and low when right channel data is present. figure 23. right justified audio interface (assuming n-bit word length) left justified bclk lrclk n sdi / sdo left channel right channel word length (wl) 1/fs n-1 n-2 3 2 1 msb lsb n n-1 n-2 3 2 1 msb lsb bclk lrclk n sdi / sdo left channel right channel word length (wl) right justified 1/fs n-1 n-2 3 2 1 msb lsb n n-1 n-2 3 2 1 msb lsb
50 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5.6. i 2 s format audio interface in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk trans ition. the other bits up to the lsb are then transmitted in order. figure 24. i 2 s justified audio interface (assuming n-bit word length) 5.7. data interface registers 5.7.1. audio data format control register register address bit label type default description r19 (13h) digital audio interface format (aic1) 7rsvd r0reserved 6 bclkinv rw 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted 5msrw0 master / slave mode control 1 = enable master mode 0 = enable slave mode 4lrprw0 right, left and i 2 s modes ? lrclk polarity 1 = invert lrclk polarity 0 = normal lrclk polarity 3:2 wl[1:0] rw 10 audio data word length 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 1:0 format[1:0] rw 10 audio data format select 11 = reserved 10 = i 2 s format 01 = left justified 00 = right justified table 56. aic1 register i2s bclk lrclk n sdi / sdo left channel right channel word length (wl) 1/fs n-1 n-2 3 2 1 msb lsb n n-1 n-2 3 2 1 msb lsb 1 bclk 1 bclk
51 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5.7.2. audio interface output tri-state tri is used to tri-state the adcdout, adclrck, daclrck , adcbclk, and dacbclk pins. in slave mode (mas- ter=0) only adcdout will be tr i-stated since the other pins are configured as inputs. th e tri-stated pins are pulled low with an internal pull-down resistor unless that resistor is disabled. 5.7.3. audio interface bit clock and lr clock configuration although the dac and adc interfaces implement separate bit clock and lr clock pins, it is also possible to share one or both of the clocks. the following restrictions must be observed when the bclk from one path (dac or adc) is combined with the lrclk from the other path (adc or dac) as described by th e bit clock and lr clock mode selection table below: 1. both the dac and adc must be pr ogrammed for the same sample rate 2. both the dac and adc must be programmed for the same number of clocks per frame 3. when in slave mode, the dac and adc data must be aligned relative to the provided bclk and lrclk (this is guaranteed in master mode) 4. the dac and adc must be powered down when changing the blrcm mode 5. if sharing the bclk from one path (dac or adc) and the lrclk from the other path (adc or dac), shut down both the dac and adc before programming the sample rate and clocks per frame for either. (again, both must match.) register address bit label type default description r20 (14h) audio interface control 2 (aic2) 7:6 dacdsel[1:0] rw 00 00: left dac = left i2s data; right dac = right i2s data 01: left dac = left i2s data; right dac = left i2s data 10: left dac = right i2s data; right dac = right i2s data 11: left dac = right i2s data; right dac = left i2s data 5:4 adcdsel[1:0] rw 00 00: left i2s data = left adc; right i2s data = right adc 01: left i2s data = left adc; right i2s data = left adc 10: left i2s data = right adc; right i2s data = right adc 11: left i2s data = right adc; right i2s data = left adc 3trirw0 tri-states adcdout, adclrclk, daclrclk, adcbclk, and dacbclk pins. 0 = adcdout is an out put, adclrck, daclrclk, adcbclk, and dacbclk are inputs (slave mode) or outputs (master mode) 1 = adcdout, adclrck, da clrclk, adcbclk, and dacbclk are high impedance 2:0 blrcm[2:0] rw 000 bitclock and lrclock mode. see table below table 57. aic2 register
52 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5.7.4. bit clock and lr clock mode selection ms blrcm [2:0] mode 1 1.when sharing both the bclk and lrclk between the dac and adc interfaces, both the dac and adc must be programmed for the same rate, the same number of clocks per frame, and dat a must be aligned the same with respect to lrclk. disable all converters before changing modes. dac bclk adc bclk dac lrclk adc lrclk 0 000 independent input for playback path input for record path input for playback path input for record path 0 001 independent input for playback path input for record path input for playback path input for record path 0 010 shared bclk (dac) input for playback and record unused input for playback path input for record path 0011 shared bclk & lrclk (dac) input for playback and record unused input for playback and record unused 0 100 shared bclk (dac) & lrclk (adc) input for playback and record unused unused input for playback and record 0 101 shared bclk (adc) unused input for playback and record input for playback path input for record path 0110 shared bclk (adc) & lrclk (dac) unused input for playback and record input for playback and record unused 0 111 shared bclk & lrclk (adc) unused input for playback and record unused input for playback and record 1 000 independent (off if converter off) output for playback path (off when dacs off) 2 2.dac (playback path) is off when hpl, hpr, spkl, and spkr power states are off. output for record path (off when adc off) 3 output for playback path (off when dacs off) output for record path (off when adcs off) 1 001 independent (off if all converters off) output for playback path (off when dacs and adcs off) output for record path (off when dacs and adcs off) output for playback path (off when dacs and adcs off) output for record path (off when dacs and adcs off) 1 010 shared bclk (dac) output for playback and record (stays on if either dac or adc on) unused (off) output for playback path (off if dac is off) output for record path (off when adcs off) 1011 shared bclk & lrclk (dac) output for playback and record (stays on if either dac or adc on) unused (off) output for playback and record (stays on if either dac or adc on) unused (off) 1 100 shared bclk(dac)& lrclk(adc) output for playback and record (stays on if either dac or adc on) unused (off) unused (off) output for playback and record (stays on if either dac or adc on) 1 101 shared bclk (adc) unused (off) output for playback and record (stays on if either dac or adc on) output for playback path (off if dac is off) output for record path (off when adcs off) 1110 shared bclk(adc)& lrclk(dac) unused (off) output for playback and record (stays on if either dac or adc on) output for playback and record (stays on if either dac or adc on) unused (off) 1 111 shared bclk & lrclk(adc) unused (off) output for playback and record (stays on if either dac or adc on) unused (off) output for playback and record (stays on if either dac or adc on) table 58. bit clock and lr clock mode selection
53 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 5.7.5. adc output pin state 5.7.6. audio interface control 3 register 5.8. bit clock mode the default master mode bit clock generator automatically produces a bit clock frequency based on the sample rate and word length. when enabled by setting the appropriate bcm bits, the bit clock mode (bcm) function overrides the default master mode bit clock generator to produce the bit clock frequency shown below: note that selecting a word length of 24-bits in auto mode generates 64 clocks per frame (64fs) 3.adc (record path) is off when adcl, and adcr power states are off (pga, d2s, boost power states are not considered.) tri-state (tri) record path power state adc data out pull-down (adopdd) adc data out state 0 off 0 off, pulled-low off 1 off, floating on na active 1 na 0 off, pulled-low na 1 off, floating table 59. adc data output pin state register address bit label type default description r21 (15h) audio interface control 3 (aic3) 7:6 rsvd r 0 reserved 5 adopdd rw 0 adcdout pull-down disable 0 = pull-down active when tri-stated or the adc path is powered down. 1 = pull-down always disabled 4alrpddrw0 adclrclk pull-down disable 0 = pull-down active when configured as input 1 = pull-down always disabled 3 abcpdd rw 0 adcbclk pull-down disable 0 = pull-down active when configured as input 1 = pull-down always disabled 2 ddipdd rw 0 dacdin pull-down disable 0 = pull-down active 1 = pull-down always disabled 1dlrpddrw0 daclrclk pull-down disable 0 = pull-down active when configured as input 1 = pull-down always disabled 0dbcpddrw0 dacbclk pull-down disable 0 = pull-down active when configured as input 1 = pull-down always disabled table 60. aic3 register
54 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec . the bcm mode bit clock generator produces 16, 20, or 32 bit cycles per sample. figure 25. bit clock mode note: the clock cycles are evenly distributed throughout the frame (true multiple of lrclk not a gated clock.) 5.9. control interface the registers are accessed through a seri al control interface using a multi-word protocol comprised of 8-bit words. the first 8 bits provide the device address and read/write flag. in a write cycle, the next 8 bits provide the register address; all subsequent words contain the data, corresponding to the 8 bits in each control register.the control interface oper- ates using a standard 2-wire interface, as a slave device only. 5.9.1. register write cycle the controller indicates the start of data transfer with a high to low transition on sda while scl remains high, signalling that a dev ice address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matche s the address of the acs522d01 and the r/w bit is ?0?, indicating a write, then t he acs522d01 responds by pulling sd a low on the next clock pulse (ack); otherwise, the acs522d01 returns to the id le condition to wait for a new start condition and valid address. once the acs522d01 has acknowledged a corr ect device address, the controller sends the acs522d01 register address. th e acs522d01 acknowledges the re gister address by pulling sda low for one clock pulse (ack). the controller then sends a byte of data (b7 to b0), and the acs522d01 acknowledges again by pulling sda low. when there is a low to high transition on sda while scl is high, the tr ansfer is complete. after receiving a complete address and data sequence the acs522d01 returns to the idle state. if a start or stop condition is detected out of sequenc e, the device returns to the idle condition. register address bit label type default description r23/r25 (17h/19h adc/dac sample rate control 7:6 abcm[1:0] dbcm[1:0] rw 00 bclk frequency 00 = auto 01 = 32 x fs 10 = 40 x fs 11 = 64 x fs table 61. master mode bclk frequency control register fs x 64 fs x 40 lrclk fs x 32
55 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec figure 26. 2-wire serial control interface the acs522d01 has device address d2. 5.9.2. multiple write cycle the controller may write more than one register with in a single write cycle. to write additional regis- ters, the controller will not generate a stop or star t (repeated start) comma nd after receiving the acknowledge for the second byte of information (register address and data). instead the controller will continue to send bytes of data. after ea ch byte of data is received, the regist er address is incre- mented. figure 27. multiple write cycle 5.9.3. register read cycle the controller indicates the start of data transfer with a high to low transition on sda while scl remains high, signalling that a device address and data will follow. if the device address received matches the address of the acs522d01 and the r/ w bit is ?0?, indicating a write, then the acs522d01 responds by pulling sda low on t he next clock pulse (ack); otherwise, the acs522d01 returns to the idle condition to wait for a new start condition and valid address. once the acs522d01 has acknowledged a correct address, the controller sends a restart command (high to low transition on sda while scl remains high). the controller then re-sends the devices address with the r/w bit set to ?1 ? to indicate a read cycle.the acs522d01 acknowle dges by pulling sda low for one clock pulse. the controller then receives a byte of register data (b7 to b0). for a single byte transfer, the ho st controller will not acknowledge (h igh on data line) the data byte and generate a low to high transition on sda while scl is high, completing the transfer. if a start or stop condition is detected out of sequence, the device returns to the idle condition. nw scl sda device address da[6:0] start ack register address ra[7:0] register data rd[7:0] ack ack stop nw scl sda device address da[6:0] start ack register address ra[7:0] register data rd[7:0] ack ack stop ack ack register write 1 register write 2 ... register data rd[7:0] @ra[7:0]+1 register write n register data rd[7:0] @ra[7:0]+n
56 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec figure 28. read cycle the acs522d01 has device address d2. 5.9.4. multiple read cycle the controller may read more than one register within a single read cycle. to read additional registers, the controller will not generate a stop or st art (repeated start) co mmand after sending the acknowledg e for the byte of data. instead the controller will continue to provide cl ocks and acknowled ge after each byte of receiv ed data. the codec will automat- ically increment the internal register address after each register has had its data successfully read (ack from host) but will not increment the register a ddress if the data is not rece ived correctly by the host (n ack from host) or if the bus cycle is terminated unexpe ctedly (however th e eq/filter address will be incremented even if the register address is not incremented when performing eq/filter ram reads). by automa tically incrementing the internal register address after each byte is read, all the internal registers of the codec may be read in a single read cycle. figure 29. multiple read cycle 5.9.5. device addressing and identification the acs522d01 has a default slave address of d2. however, it is someti mes necessary to use a different address. the acs522d01 has a device addre ss register for this purpose. the part itself has an 8-bit identification register and an 8-bit revision register that pr ovide device specific information for software. in addition, an 8-bit programmable subs ystem id register can allow firmware to provide a descriptive code to higher level software such as an operating system driver or application soft- ware. 5.9.5.1. device registers ? device address register register address bit label type default description r124 (7ch) devadr 7:1 addr[7:1] rw 1101001 7-bit slave address 0rsvd r0 not used - this bit is the r/nw bit in the 2-wire protocol. table 62. devadrl register nack scl sda device address da[6:0] nw start ack register address ra[7:0] register data rd[7:0] ack stop device address da[6:0] r ack restart da[6:0] nw ack ra[7:0] rd[7:0] ack ack nack da[6:0] r ack sr s p set register address read register @ ra[7:0] rd[7:0] read register @ ra[7:0] + 1 ack rd[7:0] read register @ ra[7:0] + n
57 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec ? device identification registers ? device revision register note: contact idt for device and revision information. 5.9.5.2. register reset the acs522d01 registers may be reset to their defa ult values using the reset register. writing a special, non-zero va lue to this register causes all other registers to assume their default states. device status bits will not necess arily change their values dependi ng on the state of the device. register address bit label type default description r126 (7eh) devidh 7:0 did[15:8] r xxh 16-bit device identification number. the acs522d01 has programmable clocking that will drive different device ids for each configuration. contact idt. r125 (7dh) devidl 7:0 did[7:0] r xxh table 63. devid h&l registers register address bit label type default description r127 (7fh) revid 7:4 maj[3:0] r xh 4-bit major revision number. contact idt. 3:0 mnr[3:0] r xh 4-bit minor revision number. contact idt. table 64. revid register register address bit label type default description r128 (80h) reset 7:0 reset[7:0] rw 00h reset register writing a value of 85h will cause registers to assume their default values. reading this register returns 00h table 65. reset register
58 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 6. audio clock generation 6.1. internal clock generation (aclk) in addition to provid ing external clocks, the p ll block will also provide tw o clocks for the audio por- tion of the device. they are ? 122.880 mhz (2560 x 48 khz) ? 112.896 (2560 x 44.1 khz) it is important that the crystal os cillator and need ed plls remain on until all audio functions, includ- ing jack detection, are disabled. 6.2. aclk clocking and sample rates the acs522d01 utilizes in ternal plls to generate the audio master clock (aclk) at 56.448mhz (22. 5792mhz *2.5) and 61.44mhz (24.576 *2.5). it then generates audio sample rates directly from the master clock. the adc and dac do not need to run at the same sample rate unless they are sharing bclk and lrclk pins. disable the appropriate converters before programming the mode or rate, especially if the dac and adc are programmed to share the same bclk and lrclk. after changing rate, a delay of up to 5m s may be needed for the part to properly lock plls, flush fil- ters, etc . register address bit label type default description r23 (17h) adc sample rate control (adcsr) 7:6 abcm[1:0] rw 00 adc bit clock mode (for data interface adcbclk generation in master mode) 00 = auto 01 = 32x fs 10 = 40x fs 11 = 64x fs 5rsvd r0reserved 4:3 abr[1:0] rw 10 adc base rate 00 = 32khz 01 = 44.1khz 10 = 48khz 11 = reserved 2:0 abm[2:0] rw 010 adc base rate multiplier 000 = 0.25x 001 = 0.50x 010 = 1x 011 = 2x 100-111 = reserved table 66. adcsr register
59 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec the clocking of the acs522d01 is controlled using the br[1:0] and bm[2:0] control bits. each value of br[1:0] + bm[2:0]selects one combination of aclk division ratios and hence one combination of sample rates the br[1:0] and bm[2:0] bits must be set to configure the appropriate adc and dac sample rates in both master and slave mode. 6.3. dac/adc modulator rate control the power consumption and audio quality may be adjusted by changing the converter modulator rate. by default the register address bit label type default description r25 (19h) dac sample rate control (dacsr) 7:6 dbcm[1:0] rw 00 dac bit clock mode (for data interface dacbclk generation in master mode) 00 = auto 01 = 32x fs 10 = 40x fs 11 = 64x fs 5rsvd r0reserved 4:3 dbr[1:0] rw 10 dac base rate 00 = 32khz 01 = 44.1khz 10 = 48khz 11 = reserved 2:0 dbm[2:0] rw 010 dac base rate multiplier 000 = 0.25x 001 = 0.50x 010 = 1x 011 = 2x 100-111 = reserved table 67. dacsr register br [1:0] bm [2:0] aclk sample rate 00 000 40.96 mhz 8 khz (mclk/5120) 001 16 khz (mclk/2560) 010 32 khz (mclk/1280) 011 reserved 100-111 reserved 01 000 56.448 mhz 11.025 khz (mclk/5120) 001 22.05 khz (mclk/2560) 010 44.1 khz (mclk/1280) 011 88.2 khz (mclk/640) 100-111 reserved 10 000 61.44 mhz 12 khz (mclk/5120) 001 24 khz (mclk/2560) 010 48 khz (mclk/1280) 011 96 khz (mclk/640) 100-111 reserved 11 000-111 - reserved table 68. aclk and sample rates
60 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec dac and adc sigma-delta modulators run at a high rate for the best audio quality. the modulator rates for the con- verters may be forced to run at half their nominal rate to conserve power. a third option allows the modulator rate to automatically drop to half rate when low sampling rates are chosen (1/2 or 1/4 the base ra te.) the dacs and adcs are independently controlled. register address bit label type default description r31 (1fh) config0 7:6 asdm[1:0] rw 10h adc modulator rate 00 = reserved 01 = half 10 = full 11 = auto 5:4 dsdm[1:0] rw 10h dac modulator rate 00 = reserved 01 = half 10 = full 11 = auto 3:2 rsvd r 0h reserved for future use. 1 dc_bypass rw 0 1 = bypass dc removal filter (warning dc content can damage speakers) 0 sd_force_on r 0 1 = supply detect forced on. 0 = supply detect on when needed (cop, uvlo enabled). table 69. config0 register dsdm[1:0] asdm[1:0] bm [2:0] modulator rate 00 na reserved 01 000 (1/4x) half 001 (1/2x) 010 (1x) 011 (2x) 10 000 (1/4x) full 001 (1/2x) 010 (1x) 011 (2x) 11 000 (1/4x) auto (half) 001 (1/2x) auto (half) 010 (1x) auto (full) 011 (2x) auto (full) table 70. sdm rates
61 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 7. characteristics 7.1. electrical specifications 7.1.1. absolute maximum ratings stresses above the ratings listed below can ca use permanent damage to the acs522d01. these ratings, which are standard values for idt commer cially rated parts, are stress ratings only. func- tional operation of the device at these or any ot her conditions above those indicated in the opera- tional sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods can af fect product reliability. electrical para meters are guarant eed only over the recommended operating temperature range. 7.1.2. recommended operating conditions item maximum rating voltage on any pin relative to ground vss - 0.3v to vdd + 0.3v operating temperature 0 o c to 70 o c storage temperature -55 o c to +125 o c soldering temperature 260 o c micbias output current 3ma amplifier maximum supply voltage 6 volts = pvdd audio maximum supply voltage 3 volts = avdd/cpvdd digital i/o maximum supply voltage 3.6 volts = dvdd_io digital core maximum supply voltage 2.0 volts = dvdd table 71. electrical speci fication: maximum ratings parameter min. typ. max. units power supplies dvdd_core 1.4 2.0 v dvdd_io 1.4 3.5 avdd/cpvdd 1.7 2.0 pvdd 3.0 5.25 v ambient operating temperature analog - 5 v 0 25 70 o c case temperature t case 90 o c table 72. recommended operating conditions esd: the acs522d01 is an esd (electrostatic discharge) sensitive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 volts without detection. even though the acs522d01 implements internal esd protection circuitry, proper esd precautions sh ould be followed to avoid damaging the functionality or performance.
62 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 7.2. device characteristics (t ambient = 25 oc, dvdd_core=dvdd_io=avdd=1.9v, pvdd=3.6v, 997hz signal, fs=48khz, input gain=0db, 24-bit audio ) parameter symbol test conditions min typ max unit analog inputs (l in1 , l in2, l in3, r in1 , r in2, r in3 ) full scale input voltage v fsiv l/r in1,2,3 single ended 0.5 -6 vrms dbv l/r in1,2,3 differential mic 0.5 -6 vrms dbv input impedance 50 kohm input capacitance 10 pf analog input boost amplifier programmable gain min 0.0 db programmable gain max 30.0 db programmable gain step size 10.0 db analog input pga programmable gain min -17.25 db programmable gain max 30.0 db programmable gain step size guaranteed monotonic 0.75 db digital volume co ntrol amplifier programmable gain min -97 db programmable gain max 30.0 db programmable gain step size guaranteed monotonic 0.5 db mute attenuation -999 db analog inputs (l in1 /r in1 , l in2 /r in2 differential) to adc signal to noise ratio snr a-weighted 20-20khz 90 db total harmonic distortion + noise thd+n -1dbfs input -80 0.01 db % analog inputs (l in1 , l in2, l in3, r in1 , r in2, r in3 single ended) to adc signal to noise ratio snr a-weighted 20-20khz 90 db total harmonic distortion + noise thd+n -1dbfs input -80 0.01 db % adc channel separation 997hz full scale signal 70 db channel matching 997hz signal 2 % dac to line-out (hpl, hpr with 10k / 50pf load) signal to noise ratio 1 snr a-weighted 102 db total harmonic distortion +noise 2 thd+n 997hz full scale signal -84 db channel separation 997hz full scale signal 70 db mute attenuation -999 db headphone outputs (hpl, hpr) full scale output level v fsov rl = 10kohm 1.0 vrms r l = 16ohm 0.75 vrms output power p o 997hz full scale signal, r l = 16ohm 35 mw (ave) signal to noise ratio snr a-weighted, r l = 16ohm 102 db table 73. device characteristics
63 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec total harmonic distortion +noise thd+n r l = 16ohms, -3dbfs -76 db r l = 32ohms, -3dbfs -78 db analog voltage reference levels charge pump output v- -5% -avdd +100mv +5% v microphone bias bias voltage v micbias -2.5- v bias current source 3ma power supply rejection ratio psrr micbias 3.3v 64 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 7.3. typical power consumption 7.4. low power mode power consumption table 75. low power mode power consumption low power settings 1) dac/adc modulators set to half rate 2) constant output power function disabled 3) all unused functions disabled (for example, input pga, input mux, and adc disabled for playback tests) 4) register 0x73=0x06 5) register 0x75=0x02 6) pll block power consumption not included mode avdd (v) pvdd (v) dvdd_io dvdd_core (v) i avdd (ma) i pvdd (ma) i dvdd_i o (ma) i dvdd_co re (ma) p total (mw) notes playback to headphone only 1.9 3.6 1.9 11 0 2 8 40 full scale 1vrms/10kohm, does not include pll/clock buffer section. fs=48khz, stereo. playback to headphone only 1.9 3.6 1.9 60 0 2 8 133 full scale 800mvrms/16ohm; does not include pll/clo ck buffer section. fs=48khz, stereo. record only 1.9 3.6 1.9 8 0 2 6 28 full scale 500mvrms; does not include pll/clock buffer section. fs=48khz, stereo. table 74. typical power consumption mode avdd (v) pvdd (v) dvdd_io dvdd_core (v) i avdd (ma) i pvdd (ma) i dvdd_i o (ma) i dvdd_co re (ma) p total (mw) notes playback to headphone only 1.9 3.6 1.9 7 <1 2 7 29 full scale 1vrms/10kohm, does not include pll/clock buffer section. fs=48khz, stereo. playback to headphone only 1.9 3.6 1.9 49 <1 2 7 110 full scale 707mvrms/16ohm/1%; does not include pll/clock buffer section. fs=48khz, stereo. record only 1.9 3.6 1.9 3 0 1 5 17 full scale 500mvrms; does not include pll/clock buffer section. fs=48khz, stereo. record only 1.9 3.6 1.9 3 0 <1 4 12 full scale 500mvrms; does not include pll/clock buffer section. fs=8khz, stereo.
65 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 8. register map register (d15:9) name remarks bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default r0 (00h) hpvoll left hp volume hpvol_l[6:0] 77h r1 (01h) hpvolr right hp volume hpvol_r[6:0] 77h r2 (02h) reserved rsvd 6fh r3 (03h) reserved rsvd 6fh r4 (04h) dacvoll left dac volume dacvol_l[7:0] ffh r5 (05h) dacvolr right dac volume dacvol_r[7:0] ffh r6 (06h) adcvoll left adc volume adcvol_l[7:0] bfh r7 (07h) adcvolr right adc volume adcvol_r[7:0] bfh r8 (08h) involl left input volume izcl invol_l 17h r9 (09h) involr right input volume izcr invol_r 17h r10 (0ah) vuctl volume update control adcfade dacfade involu adcvolu dacvolu hpvolu c0h r11 (0bh) inmode adc input mode ds 00h r12 (0ch) insell adcl signal path insel_l[1:0] micbst_l[1:0] 00h r13 (0dh) inselr adcr signal path insel_r[1:0] micbst_r[1:0] 00h r14 (0eh) alc0 alc0 alc mode alcsel[1:0] 00h r15 (0fh) alc1 alc1 maxgain[2:0] alcl[3:0] 7bh r16 (10h) alc2 alc2 mingain[2:0] hld[3:0] 00h r17 (11h) alc3 alc3 dcy[3:0] atk[3:0] 32h r18 (12h) ngate noise gate ngth[4:0] ngg[1:0] ngat 00h r19 (13h) aic1 audio interface 1 bclkinv ms lrp wl[1:0] format[1:0] 0ah r20 (14h) aic2 audio interface 2 dacdsel[1:0] adcdsel[1:0] tri blrcm[2:0] 00h r21 (15h) aic3 audio interface 3 adopdd alrpdd abcpdd ddipdd dlrpdd dbcpdd 00h r22 (16h) cnvrtr0 adc control adcpolr adcpoll amonomix[1:0] adcmu hpor adchpdr adchpdl 08h r23 (17h) adcsr adc sample rate abcm[1:0] abr[1:0] abm[2:0] 12h r24 (18h) cnvrtr1 dac control dacpolr dacpoll dmonomix[1:0] dacmu deemph 08h r25 (19h) dacsr dac sample rate dbcm[1:0] dbr[1:0] dbm[2:0] 12h r26 (1ah) pwrm1 pwr mgmt (1) bstl bstr pgal pgar adcl adcr micb digenb 00h r27 (1bh) pwrm2 pwr mgmt (2) d2s hpl hpr vref 00h r28 (1ch) ctl additional control hpswen hpswpol eq2sw1 eq2sw0 eq1sw1 eq1sw0 tsden toen 00h r29 (1dh) thermts temp sensor control triphighstat triplowstat tripsplit[1:0] tripshift[1:0] poll[1:0] 09h r30 (1eh) reserved rsvd 81h r31 (1fh) config0 config0 asdm1 asdm0 dsdm1 dsdm0 dc_bypass sd_force_on a0h r32 (20h) config1 config1 eq2_en eq2_be2 eq2_be1 eq2_be0 eq1_en eq1_be2 eq1_be1 eq1_be0 00h r33 (21h) gainctl gain control zerodet_flag zerodetlen1 zerodetlen0 auto_mute 24h r34 (22h) cop1 constant output power1 copatten copgain hdeltaen coptarget[4:0] 08h r35 (23h) cop2 constant output power2 hdcomp mode avglength[3:0] monrate[1:0] 02h r36 (24h) dmicctl d-mic control dmicen dmono dmphadj1 dmphadj0 dmrate1 dmrate0 00h r37 (25h) clectl cmplmtctl lvl_mode windowsel exp_en limit_en comp_en 00h r38 (26h) mugain clemakeupgain clemug4 clemug3 clemug2 clemug1 clemug0 00h r39 (27h) compth compressor threshold compth7 compth6 compth5 compth4 compth3 compth2 compth1 compth0 00h r40 (28h) cmprat compressor ratio cmprat4 cmprat3 cmprat2 cmprat1 cmprat0 00h r41 (29h) catktcl comp attack time const low catktc7 catktc6 catktc5 catktc4 catktc3 catktc2 catktc1 catktc0 00h r42(2ah) catktch comp attack time const high catktc15 catktc14 catktc13 catktc12 catktc11 catktc10 catktc9 catktc8 00h r43 (2bh) creltcl comp release time const low creltc7 creltc6 creltc5 creltc4 creltc3 creltc2 creltc1 creltc0 00h r44 (2ch) creltch comp release time const high creltc15 creltc14 creltc13 creltc12 creltc11 creltc10 creltc9 creltc8 00h r45 (2dh) limth limiter threshold limth7 limth 6 limth5 limth4 limth3 limth2 limth1 limth0 00h r46 (2eh) limtgt limiter target limtgt7 limtg6 limtgt5 limtgt4 limtgt3 limtgt2 limtgt1 limtgt0 00h r47 (2fh) latktcl limiter attack time constant low latkt c7 latktc6 latktc5 latktc4 latktc3 latktc2 latktc1 latktc0 00h r48 (30h) latktch limiter attack time constant high latktc15 latktc14 latktc13 latktc12 latktc11 latktc10 latktc9 latktc8 00h r49 (31h) lreltcl limiter release time constant low lreltc7 lreltc6 lreltc5 lreltc4 lreltc3 lreltc2 lreltc1 lreltc0 00h r50 (32h) lreltch limiter release time constant high lreltc15 lreltc14 lreltc13 lreltc12 lreltc11 lreltc10 lreltc9 lreltc8 00h r51 (33h) expth expander threshold expth7 expt h6 expth5 expth4 expth3 expth2 expth1 expth0 00h r52 (34h) exprat expander ratio exprat2 exprat1 exprat0 00h table 76. register map
66 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec note: ? registers not described in this map should be considered ?reserved?. ? numerous portions of the register map are compat ible with popular codecs from other vendors. r53 (35h) xatktcl expander attack time constant low xatktc7 xatktc6 xatktc5 xatktc4 xatktc3 xatktc2 xatktc1 xatktc0 00h r54 (36h) xatktch expander attack time constant high xatktc15 xatktc14 xatktc13 xatktc12 xa tktc11 xatktc10 xatktc9 xatktc8 00h r55 (37h) xreltcl expander release time constant low xreltc7 xreltc6 xreltc5 xreltc4 xreltc3 xreltc2 xreltc1 xreltc0 00h r56 (38h) xreltch expander release time constant high xreltc15 xreltc14 xreltc13 xreltc12 xreltc11 xreltc10 xreltc9 xreltc8 00h r57 (39h) fxctl effects control 3den teen tnlfbyp been bnlfbyp 00h r58 (3ah) daccrwrl daccram_write_lo daccrwd[7:0] 00h r59 (3bh) daccrwrm daccram_write_mid daccrwd[15:8] 00h r60 (3ch) daccrwrh daccram_write_hi daccrwd[23:16] 00h r61 (3dh) daccrrdl daccram_read_lo daccrrd[7:0] 00h r62 (3eh) daccrrdm daccrram_read_mid daccrrd[15:8] 00h r63 (3fh) daccrrdh daccrram_read_hi daccrrd[23:16] 00h r64 (40h) daccraddr daccram_addr daccradd[7:0] 00h r65 (41h) dcofsel dc_coef_sel dc_coef_sel[2:0] 05h r66-123 rsvd rsvd na r124(7ch) devadr i2c device address addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 d2h r125(7dh) devidl device idlow did7 di d6 did5 did4 did3 did2 did1 did0 xxh 1 r126(7eh) devidh device id high did15 did14 did13 did12 did11 did10 did9 did8 xxh 1 r127(7fh) revid device revision maj3 maj2 maj1 maj0 mnr3 mnr2 mnr1 mnr0 xxh 2 r128(80h) reset reset writing 0x85 to this register resets all registers to their default state 00h r129-r135 (81h - 87h) reserved rsvd na r136(88h) reserved rsvd 08h r137-r255 (88h-ffh) reserved rsvd na 1. device id is dependent upon clock programming. 2. for device revision information, please contact idt. register (d15:9) name remarks bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default table 76. register map
67 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 9. pinout figure 30. acss522d01 pinout top view acs522d01 afilt1 vref hp_det pvdd cpgnd cap+ dvdd core afilt2 hp r avss1 lin1 lin2 dvss avdd2 hp l rin1 rin2 avss2 dvdd io dac bclk pvdd test dmic_ dat dmic_ clk dac din dac lrclk vdd_ clk mclk sda adc lrclk scl adcd out vss_ clk vss_pll vdd_ pll1 adc bclk cpvdd micbias avdd1 v- cap- a b c d e f 1234567
68 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 9.1. pin tables 9.1.1. power pins to ta l p i n s : 1 8 9.1.2. reference pins to ta l p i n s : 4 pin name pin function i/o internal pull-up pull-down pin location pvdd btl supply i(power) none f5, e2 dvdd core dsp and other core logic+clocks i(power) none a3 dvddio interface (i 2 s, i 2 c, gpio) i(power) none a5 dvss digital return i(power) none a4 avdd analog core supply i(power) none b4, e1 avss analog return i(power) none c4, e3 cpvdd charge pump supply i(power) none b1 cap+ flying cap i/o(power) none c2 cap- flying cap i/o(power) none c1 v- negative analog supply (bypass cap) o(power) none d1 cpgnd charge pump group i(power) none d2 vdd_pll1 pll supply i(power) none d7 vdd_clk clock supply i(power) none f6 vss_pll pll return i(power) none e7 vss_clk clock return i(power) none f7 table 77. power pins pin name pin function i/o internal pull-up pull-down pin location micbias 2.5v 1.5 ma microphone bias o(analog) none f1 afilt1 adc input filter cap i(analog) none a2 afilt2 adc input filter cap i(analog) none b3 vref vref reference pin (bypass) i(analog) none b2 table 78. reference pins
69 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 9.1.3. analog input pins to ta l p i n s : 6 9.1.4. analog output pins to ta l p i n s : 2 9.1.5. data and control pins to ta l p i n s : 1 0 pin name pin function i/o internal pull-up pull-down pin location lin1 left input #1 i(analog) none d3 rin1 right input #1 i(analog) none e4 lin2 left input #2 i(analog) none c3 rin2 right input #2 i(analog) none d4 dmic_clk digital mic clock for acs522d01 i(analog) none c5 dmic_dat digital mic data for acs522d01 i(analog) none d5 table 79. analog input pins pin name pin function i/o internal pull-up pull-down pin location hp out l headphone output o(analog) none f4 hp out r headphone output o(analog) none f3 table 80. analog output pins pin name pin function i/o internal pull-up pull-down pin location adcbclk adc i 2 s shift clock i/o(digital) pull-down c7 adclrclk adc i 2 s framing clock i/o(digital) pull-down c6 adcdout adc i 2 s output data o(digital) pull-down b7 dacbclk dac i 2 s shift clock i/o(digital) pull-down b5 daclrclk dac i 2 s framing clock i/o(digital) pull-down b6 dacdin dac i 2 s input data i(digital) pull-down a6 i2c_scl scl i 2 c shift clock i(digital) pull-up a7 i2c_sda sda i 2 c shift data i(digital) pull-up d6 hp_det headphone jack detection i(digital) pull-up f2 test reserved test pin i(analog) none e5 table 81. data and control pins
70 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 9.1.6. clock and no connect pins to ta l p i n s : 1 10. package information 10.1. package diagram figure 31. package drawing pin name pin function i/o internal pull-up pull-down pin location mclk master clock clock none e6 table 82. clock and no connect pins
71 v1.0 1/12 ?2011 integrated device technology, inc. acs522d01 acs522d01 low-power, high-fidelity, integrated codec 11. application information for application information, please see refere nce designs and applicat ion notes available on www.idt.com. 12. ordering information yy = silicon revision, contact idt for current part number. 13. disclaimer while the information pres ented herein has been ch ecked for both accuracy and reliability, manufac- turer assumes no responsibility for ei ther its use or for th e infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal co mmercial applications. any other applications, such as those requiring extended temper ature range, high relia bility, or other extr aordinary environmental requirements, are not recommended without additional processing by manufacturer. manufacturer reserves the right to change any circuitry or spec ifications without notice. manufacturer does not authorize or warrant any product for use in life support devices or critical medical instruments. ACS522D01AHGYYX 41-ball wlcsp rohs package
acs522d01 low-power, high-fidelity, integrated codec 6024 silver creek valley road san jose, california 95138 disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to modify the products and/or specif ications de- scribed herein at any time and at idt?s sole discretion. all info rmation in this document, including descriptions of product fe atures and perfor- mance, is subject to change without notice. performance specific ations and the operating parameters of the described products a re determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, t he suitability of idt?s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the intellectual property r ights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, in- cluding protected names, logos and designs, are the propert y of idt or their respective third party owners. 14. document revision history revision date description of change 0.5 april 2011 initial release 0.51 june 2011 updated registers for zb silicon. r136 default to 08h, r34 default to 08h, r27 bits 1:2 now reserved. r16, r8, r9 bit 7 now reserved. r31 bit 0 now sd_force_on. front page description and target applications updated. 0.52 june 2011 added package diagram 0.7 july 2011 updated pinout and package drawing. added low power mode typical power consumption table and updated standard typical values. removed app lications section, see reference design and application notes on www.idt.com, updates to the electrical characteristics. compressor/limiter configuration section separated. 0.8 september 2011 updated acs522a01 pin table to reflect lin3 and rin3 pins. also updated acs522d01 pin table to reflect cap+ pin. 0.9 november 2011 removed separate analog microphone device. the acs522d01 has 2 analog inputs that can be used for analog microphones. changed 40mw to 35mw on headphone output and changed power supply rejection ration maximum from 5.5 v to 5.25 v. 1.0 january 2012 corrected the i/o type for the analog output pins.

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